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[SI-LIST] Re: SI-LIST] Re: Questions about interplane capacitance
- From: Istvan Novak <istvan.novak@xxxxxxxxxxx>
- To: Ihsan Erdin <erdinih@xxxxxxxxx>
- Date: Sun, 16 Mar 2008 10:25:22 -0400
Ihsan,
No, I did not say that and it is not supposed to be that way. What
makes the difference
is the way how the signal propagates in the different structures: in
one-dimensional
transmission lines your description is correct. In two-dimensional
transmission lines
the wave spreads radially. You can find the description of radial
transmission lines
in a number of good textbooks, for instance in the widely cited Ramo:
Fields and Waves...
(look for Section 9.3...)
regards,
Istvan
Ihsan Erdin wrote:
> Istvan,
>
> In a lossless TEM structure, be it a linear, planar or biconical
> transmission line, the multiplication of the per-unit-length
> parameters C and L always results in [epsilon x mu]. Keeping the
> inductance constant while increasing the capacitance is tantamount to
> saying that this value changes with radial distance from the source.
> Since 1/sqrt(LC) is the speed of the wavefront that means wave is
> propagating slower and slower as the plane size grows. As the plane
> size approaches infinity the light in it will almost come to a stop!
> Do you really mean that?
>
> Regards
>
> Ihsan
>
> On Sat, Mar 15, 2008 at 11:24 PM, Istvan Novak <istvan.novak@xxxxxxxxxxx>
> wrote:
>
>> Kevin,
>>
>> There are several ways to approximate the characteristic impedance of
>> planes. In one approach we can say that the inductance is constant (the
>> sheet inductance) whereas capacitance grows with the square as you
>> linearly grow the plane shape. Another approach is to use the
>> propagation delay across the plane, which grows linearly with the
>> increase of plane. From the delay and static capacitance we can
>> calculate the characteristic impedance. Either way, the impedance goes
>> down as the plane grows.
>>
>> Regarding to capacitor placement; my comment was that location matters
>> (and you want to put them close to the active device) IF the planes are
>> not matched terminated. The approach of 'sprinkling' the board with
>> bypass capacitors also can be made to work. It is also called
>> area-capacitor approach, when you place capacitors on the plane at
>> regular intervals, close enough that the resonance cavities between
>> adjacent capacitors give high enough resonance frequencies that you dont
>> need to worry about them (numerically it is linked to the highest
>> frequency of interest, which increases as rise times fall and our
>> signaling speeds go up). Area capacitors create a loaded plane
>> structure, which becomes a periodical transmission-line filter: beyond a
>> cutoff frequency it attenuates the noise trying to propagate on the
>> planes. This filtering is the benefit of sprinkling; the price is: more
>> parts.
>>
>>
>>
>> Regards,
>>
>> Istvan Novak
>> SUN Microsystems
>>
>> Jennings, Kevin F wrote:
>> > Istvan,
>> >
>> >
>> > I'm missing how the size of the board would affect the plane impedance.
>> Are you saying that the 32pH and 1nF per square for L and C are functions of
>> the overall size and therefore not basically constant? I understand that
>> the larger planes would increase both L and C but since Z depends on the
>> ratio L/C then it seems that Z would be constant to the extent that the
>> pH(nF) per square approximation is valid. Could you clarify?
>> >
>> >
>> >
>> > Also, you mention that the location of caps matter, and you want to put
>> them as close as possible to the active devices as possible. Do you
>> understand the rationale behind those that advocate putting the caps evenly
>> spaced around the plane area? (I don't...unless all the active devices tend
>> to draw the same current).
>> >
>> >
>> >
>> > Kevin Jennings
>> >
>> >
>> >
>> >
>> >> Kevin,
>> >>
>> >
>> >
>> >
>> >
>> >> Yes, not all power rails are well suited for matched distribution. Keep
>> >>
>> >
>> >
>> >> in mind, however, that
>> >>
>> >
>> >
>> >> the approximate plane impedance goes down as the plane size goes up. On
>> >>
>> >
>> >
>> >> medium and large
>> >>
>> >
>> >
>> >> boards, assuming standard PCB technology, getting matched planes down to
>> >>
>> >
>> >
>> >> the 10 milliohm
>> >>
>> >
>> >
>> >> range is feasible. If you need lower impedance, you will need to use
>> >>
>> >
>> >
>> >> non-matched planes and
>> >>
>> >
>> >
>> >> in that case the location of capacitors does matter: you want to put as
>> >>
>> >
>> >
>> >> close to the active
>> >>
>> >
>> >
>> >> device(s) as possible.
>> >>
>> >
>> >
>> >
>> >
>> >> Regards,
>> >>
>> >
>> >
>> >
>> >
>> >> Istvan Novak
>> >>
>> >
>> >
>> >> SUN Microsystems
>> >>
>> >
>> >
>> >
>> >
>> >
>> > Jennings, Kevin F wrote:
>> >
>> >
>> >> Istvan,
>> >>
>> >
>> >
>> >
>> >
>> >> For the garden variety PCB material Er ~4, a 1 inch by 1 inch square
>> will h=
>> >>
>> >
>> >
>> >> ave C ~ 1nF per mil thickness and L ~32pH per mil thickness (both Dr.
>> Eric =
>> >>
>> >
>> >
>> >> B's approximations) giving the following characteristic impedances as a
>> fun=
>> >>
>> >
>> >
>> >> ction of dielectric thickness
>> >>
>> >
>> >
>> >
>> >
>> >> H(mils) Z(ohms)
>> >>
>> >
>> >
>> >> ------ ----
>> >>
>> >
>> >
>> >> 1 0.18
>> >>
>> >
>> >
>> >> 2 0.36
>> >>
>> >
>> >
>> >> 3 0.54
>> >>
>> >
>> >
>> >> 4 0.72
>> >>
>> >
>> >
>> >> 5 0.89
>> >>
>> >
>> >
>> >
>> >
>> >> Assuming you need to keep voltage regulation to within 5%, then the
>> maximum=
>> >>
>> >
>> >
>> >> amount of current you'll be able to draw as a function of dielectric
>> thick=
>> >>
>> >
>> >
>> >> ness will be .05 / Z
>> >>
>> >
>> >
>> >
>> >
>> >> H Z dI(Amps)
>> >>
>> >
>> >
>> >> -- ---- --------
>> >>
>> >
>> >
>> >> 1 0.18 0.280
>> >>
>> >
>> >
>> >> 2 0.36 0.140
>> >>
>> >
>> >
>> >> 3 0.54 0.093
>> >>
>> >
>> >
>> >> 4 0.72 0.070
>> >>
>> >
>> >
>> >> 5 0.89 0.056
>> >>
>> >
>> >
>> >
>> >
>> >> Or did I miss something entirely?
>> >>
>> >
>> >
>> >
>> >
>> >> Interesting technique even if it might only be applicable for relatively
>> lo=
>> >>
>> >
>> >
>> >> w power situations.
>> >>
>> >
>> >
>> >
>> >
>> >> Kevin Jennings
>> >>
>> >
>> >
>> >
>> >
>> >
>> >
>> >>> Date: Fri, 14 Mar 2008 08:57:57 -0400
>> >>>
>> >
>> >
>> >>> From: Istvan Novak <istvan.novak@xxxxxxxxxxx>
>> >>>
>> >
>> >
>> >>> Subject: [SI-LIST] Re: Antwort: Re: Questions about interplane
>> >>>
>> >
>> >
>> >>> capacitance
>> >>>
>> >
>> >
>> >
>> >
>> >>> Joel,
>> >>>
>> >
>> >
>> >
>> >
>> >>> Imagine the following. You establish your impedance target. For sake
>> >>>
>> >
>> >
>> >>> of simplicity lets assume you have a single load (a single pin) to
>> >>>
>> >
>> >
>> >>> feed with clean power.
>> >>>
>> >
>> >
>> >>> We know from
>> >>>
>> >
>> >
>> >>> previous analysis that minimizing the worst-case transient
>> >>>
>> >
>> >
>> >>> peak-to-peak noise can be done by setting the impedance target to be
>> >>>
>> >
>> >
>> >>> flat within the frequency range of interest.
>> >>>
>> >
>> >
>> >>> For sake of simplicity lets assume the frequency range of interest is
>> >>>
>> >
>> >
>> >>> from DC to Fmax.
>> >>>
>> >
>> >
>> >>> On a circuit schematics your ideal PDN solution is a series R-L source
>> >>>
>> >
>> >
>> >>> impedance, where R is your impedance target, and L is such that
>> >>>
>> >
>> >
>> >>> Fmax=3D1/(2*PI*L/R).
>> >>>
>> >
>> >
>> >>> If the
>> >>>
>> >
>> >
>> >>> PDN design is done properly, the load-current fluctuations will create
>> >>>
>> >
>> >
>> >>> only acceptably small voltage noise on the supply rail, in other words
>> >>>
>> >
>> >
>> >>> the load impedance is much greater than R, so your source operates in
>> >>>
>> >
>> >
>> >>> the 'unloaded' mode.
>> >>>
>> >
>> >
>> >
>> >
>> >>> To turn the ideal schematics into an actual circuit, you can choose
>> >>>
>> >
>> >
>> >>> from a large number of methods to synthesize the source impedance.
>> >>>
>> >
>> >
>> >>> One attractive option is to take a transmission line of characteristic
>> >>>
>> >
>> >
>> >>> impedance of R, match it at both ends, and to connect one end to the
>> >>>
>> >
>> >
>> >>> DC source, the other end to your load. The required PDN impedance
>> >>>
>> >
>> >
>> >>> (R) is usually
>> >>>
>> >
>> >
>> >>> way lower than 50 ohms, so this is not your typical coax cable or
>> >>>
>> >
>> >
>> >>> signal trace, but the physics is the same regardless of the
>> >>>
>> >
>> >
>> >>> characteristic impedance: a terminated transmission line shows its
>> >>>
>> >
>> >
>> >>> characteristic impedance regardless of its length and frequency. For
>> >>>
>> >
>> >
>> >>> PDN analysis, the characteristic impedance can be considered constant
>> >>>
>> >
>> >
>> >>> even if we have losses and dispersion. The transmission line is a
>> >>>
>> >
>> >
>> >>> distributed R-L-G-C network, where even if we neglect R and G, the
>> >>>
>> >
>> >
>> >>> signal propagates through the series of capacitive and inductive
>> >>>
>> >
>> >
>> >>> contributors. The approximate characteristic impedance is sqrt(L/C)
>> >>>
>> >
>> >
>> >>> and the approximate propagation delay is sqrt(L*C). If you take this
>> >>>
>> >
>> >
>> >>> terminated transmission line, it will show
>> >>>
>> >
>> >
>> >>> R/2 impedance at the load point, regardless of its length and delay.
>> >>>
>> >
>> >
>> >>> If the load current fluctuates (within the bandwidth of Fmax), the
>> >>>
>> >
>> >
>> >>> voltage fluctuation will be R/2*I(t).
>> >>>
>> >
>> >
>> >>> (note: when you consider a one-dimensional transmission line, matched
>> >>>
>> >
>> >
>> >>> at both ends, your actual impedance shown to the load is R/2, unless
>> >>>
>> >
>> >
>> >>> you use source termination only, which gives you an impedance of R).
>> >>>
>> >
>> >
>> >
>> >
>> >>> In the above circuit, the charge flows continuously from source to
>> >>>
>> >
>> >
>> >>> load, and delay does not matter.
>> >>>
>> >
>> >
>> >
>> >
>> >>> The key to the above simplistic picture is the matching: if we
>> >>>
>> >
>> >
>> >>> consider bypass capacitors, those must have resistances properly
>> >>>
>> >
>> >
>> >>> matching the plane structure's characteristic impedance.
>> >>>
>> >
>> >
>> >>> I call them Bypass Resistors, because it is really their resistance
>> >>>
>> >
>> >
>> >>> what
>> >>>
>> >
>> >
>> >>> matters: C and L
>> >>>
>> >
>> >
>> >>> are less important. C is there only to make sure we do not draw DC
>> >>>
>> >
>> >
>> >>> current with the termination (so it should be as high value as
>> >>>
>> >
>> >
>> >>> possible), and L is there as physical reality, so it should be as low
>> >>>
>> >
>> >
>> >>> as conveniently possible.
>> >>>
>> >
>> >
>> >
>> >
>> >>> Regards,
>> >>>
>> >
>> >
>> >
>> >
>> >>> Istvan Novak
>> >>>
>> >
>> >
>> >>> SUN Microsystems
>> >>>
>> >
>> >
>> >
>> >
>> >
>> >
>> >>> Joel Brown wrote:
>> >>>
>> >
>> >
>> >
>> >
>> >>>> I hate to prolong this but...
>> >>>>
>> >
>> >
>> >>>> When I think about a transmission line in the normal sense (signal
>> >>>>
>> >
>> >
>> >>>> propagation), A driver switches at one end but initially all it sees
>> >>>>
>> >
>> >
>> >>>> is
>> >>>>
>> >
>> >
>> >
>> >
>> >>> Zo
>> >>>
>> >
>> >
>> >
>> >
>> >>>> which looks like a resistor maybe 50 ohms and it does not even see
>> >>>>
>> >
>> >
>> >>>> the
>> >>>>
>> >
>> >
>> >
>> >
>> >>> load
>> >>>
>> >
>> >
>> >
>> >
>> >>>> until wave propagates the length of the line. So there is a time delay.
>> >>>>
>> >
>> >
>> >
>> >
>> >>> Now
>> >>>
>> >
>> >
>> >
>> >
>> >>>> think of the driver being the power pin of the IC and the load being
>> >>>>
>> >
>> >
>> >>>> the bypass cap on the corner of the board or visa versa and I see a
>> >>>>
>> >
>> >
>> >
>> >
>> >>> propagation
>> >>>
>> >
>> >
>> >
>> >
>> >>>> delay, so what am I missing?
>> >>>>
>> >
>> >
>> >
>> >
>> >>>> Joel
>> >>>>
>> >
>> >
>> >
>> >
>> >
>> >
>> >>>> -----Original Message-----
>> >>>>
>> >
>> >
>> >>>> From: SILR [mailto:silr@xxxxxxxxxxxx]
>> >>>>
>> >
>> >
>> >>>> Sent: Thursday, March 13, 2008 6:27 PM
>> >>>>
>> >
>> >
>> >>>> To: 'steve weir'; 'Joel Brown'
>> >>>>
>> >
>> >
>> >>>> Cc: 'Istvan Novak'; si-list@xxxxxxxxxxxxx
>> >>>>
>> >
>> >
>> >>>> Subject: RE: [SI-LIST] Re: Antwort: Re: Questions about interplane
>> >>>>
>> >
>> >
>> >>>> capacitance
>> >>>>
>> >
>> >
>> >
>> >
>> >>>> Joel asked:
>> >>>>
>> >
>> >
>> >>>> <<< ...why is charge propagation velocity not a factor when the PDN
>> >>>>
>> >
>> >
>> >>>> is purely resistive? >>>
>> >>>>
>> >
>> >
>> >
>> >
>> >
>> >
>> >>>> Well, here's a crazy way to think about this (which I'm sure not
>> >>>>
>> >
>> >
>> >
>> >
>> >>> everyone
>> >>>
>> >
>> >
>> >
>> >
>> >>>> will agree)... I guess this would be like how Eric B. might put it...
>> >>>>
>> >
>> >
>> >
>> >
>> >>> "Be
>> >>>
>> >
>> >
>> >
>> >
>> >>>> the Signal"
>> >>>>
>> >
>> >
>> >
>> >
>> >
>> >
>> >>>> I'm the charge on some corner of a board...there's an IC in the
>> >>>>
>> >
>> >
>> >>>> middle
>> >>>>
>> >
>> >
>> >
>> >
>> >>> of
>> >>>
>> >
>> >
>> >
>> >
>> >>>> the board...
>> >>>>
>> >
>> >
>> >
>> >
>> >>>> I have to get to that IC using this transmission line called the PDN.
>> >>>>
>> >
>> >
>> >
>> >
>> >>> If
>> >>>
>> >
>> >
>> >
>> >
>> >>>> this Transmission Line had the classical Ls and Cs (and Rs) to
>> >>>>
>> >
>> >
>> >>>> describe
>> >>>>
>> >
>> >
>> >
>> >
>> >>> its
>> >>>
>> >
>> >
>> >
>> >
>> >>>> characteristics, then that means I have to deal with changing EM
>> >>>>
>> >
>> >
>> >>>> fields
>> >>>>
>> >
>> >
>> >
>> >
>> >>> to
>> >>>
>> >
>> >
>> >
>> >
>> >>>> get to that IC... but these time varying EM fields always cause
>> >>>>
>> >
>> >
>> >>>> some
>> >>>>
>> >
>> >
>> >
>> >
>> >>> delay
>> >>>
>> >
>> >
>> >
>> >
>> >>>> in my charge getting to that IC in a timely manner...
>> >>>>
>> >
>> >
>> >
>> >
>> >>>> BUT!!! ...if this Transmission Line had nothing but Rs (no Ls and
>> >>>>
>> >
>> >
>> >>>> Cs) to describe its characteristics then that means I don't have to
>> >>>>
>> >
>> >
>> >>>> deal with
>> >>>>
>> >
>> >
>> >
>> >
>> >>> time
>> >>>
>> >
>> >
>> >
>> >
>> >>>> varying EM fields any longer... I just have to deal with resistive
>> >>>>
>> >
>> >
>> >
>> >
>> >>> losses
>> >>>
>> >
>> >
>> >
>> >
>> >>>> only but this only equates to a drop in Static Voltage Potential and
>> >>>>
>> >
>> >
>> >
>> >
>> >>> nothing
>> >>>
>> >
>> >
>> >
>> >
>> >>>> more... (so keep the Z low!!!) And I can get there (to the IC) in
>> >>>>
>> >
>> >
>> >>>> no
>> >>>>
>> >
>> >
>> >
>> >
>> >>> time
>> >>>
>> >
>> >
>> >
>> >
>> >>>> and the IC gets the charges that it needs and it wouldn't even know
>> >>>>
>> >
>> >
>> >
>> >
>> >>> anything
>> >>>
>> >
>> >
>> >
>> >
>> >>>> is different...
>> >>>>
>> >
>> >
>> >
>> >
>> >>>> Again, this is a crazy way to look at this... but it works for me, for
>> >>>>
>> >
>> >
>> >>>> now... until I get grilled by the senior members... :-)
>> >>>>
>> >
>> >
>> >
>> >
>> >>>> Silvester
>> >>>>
>> >
>> >
>> >
>> >
>> >>>> -----Original Message-----
>> >>>>
>> >
>> >
>> >>>> From: si-list-bounce@xxxxxxxxxxxxx
>> >>>>
>> >
>> >
>> >>>> [mailto:si-list-bounce@xxxxxxxxxxxxx]
>> >>>>
>> >
>> >
>> >
>> >
>> >>> On
>> >>>
>> >
>> >
>> >
>> >
>> >>>> Behalf Of steve weir
>> >>>>
>> >
>> >
>> >>>> Sent: Thursday, March 13, 2008 5:57 PM
>> >>>>
>> >
>> >
>> >>>> To: Joel Brown
>> >>>>
>> >
>> >
>> >>>> Cc: 'Istvan Novak'; si-list@xxxxxxxxxxxxx
>> >>>>
>> >
>> >
>> >>>> Subject: [SI-LIST] Re: Antwort: Re: Questions about interplane
>> >>>>
>> >
>> >
>> >
>> >
>> >>> capacitance
>> >>>
>> >
>> >
>> >
>> >
>> >>>> Joel, it is transmission line theory. Think about an infinitely
>> >>>>
>> >
>> >
>> >>>> long signal transmission line for a moment. At any instant a driver
>> >>>>
>> >
>> >
>> >>>> sees a constant impedance across frequency. The voltage to current
>> >>>>
>> >
>> >
>> >>>> relation is independent of prior history. What Istvan describes is
>> >>>>
>> >
>> >
>> >>>> a very low
>> >>>>
>> >
>> >
>> >
>> >
>> >>> impedance
>> >>>
>> >
>> >
>> >
>> >
>> >>>> transmission structure for power.
>> >>>>
>> >
>> >
>> >
>> >
>> >>>> Sadly, a lot of IC vendors are still playing catch-up in terms of
>> >>>>
>> >
>> >
>> >>>> power delivery. If they had their game together, they would be
>> telling=
>> >>>>
>> >
>> >
>> >
>> >
>> >> you:
>> >>
>> >
>> >
>> >
>> >
>> >>>> The actual voltage tolerances at the die, the current spectrum at
>> >>>>
>> >
>> >
>> >>>> the
>> >>>>
>> >
>> >
>> >
>> >
>> >>> die,
>> >>>
>> >
>> >
>> >
>> >
>> >>>> and the parasitics of the die and package. From that you could
>> >>>>
>> >
>> >
>> >>>> engineer your PDN. Instead often what we see are partial recipes
>> >>>>
>> >
>> >
>> >>>> like you
>> >>>>
>> >
>> >
>> >
>> >
>> >>> describe.
>> >>>
>> >
>> >
>> >
>> >
>> >>>> On a good day the recipes cost extra money. On a bad day, they
>> >>>>
>> >
>> >
>> >>>> result
>> >>>>
>> >
>> >
>> >
>> >
>> >>> in
>> >>>
>> >
>> >
>> >
>> >
>> >>>> failures.
>> >>>>
>> >
>> >
>> >
>> >
>> >>>> One can build a resistive networks several ways. One is to add
>> >>>>
>> >
>> >
>> >>>> discrete resistance by any number of methods, another is to use the
>> >>>>
>> >
>> >
>> >>>> FDTIM method
>> >>>>
>> >
>> >
>> >
>> >
>> >>> that
>> >>>
>> >
>> >
>> >
>> >
>> >>>> Larry Smith has long championed. And even though resistive networks
>> >>>>
>> >
>> >
>> >
>> >
>> >>> have
>> >>>
>> >
>> >
>> >
>> >
>> >>>> attractive qualities, reactive networks may still be cheaper and
>> >>>>
>> >
>> >
>> >>>> equally effective. It all depends on the circumstances. It is
>> >>>>
>> >
>> >
>> >>>> somewhat akin to surface finishes: there is no ideal one. But
>> >>>>
>> >
>> >
>> >>>> there are several that
>> >>>>
>> >
>> >
>> >
>> >
>> >>> when
>> >>>
>> >
>> >
>> >
>> >
>> >>>> used properly work very well. One just needs to respect the
>> >>>>
>> >
>> >
>> >>>> limitations
>> >>>>
>> >
>> >
>> >
>> >
>> >>> of
>> >>>
>> >
>> >
>> >
>> >
>> >>>> each method.
>> >>>>
>> >
>> >
>> >
>> >
>> >>>> Part of the problem figuring this stuff out is having sufficient
>> >>>>
>> >
>> >
>> >
>> >
>> >>> experience
>> >>>
>> >
>> >
>> >
>> >
>> >>>> to judge trade-offs early in the design process. That's just
>> >>>>
>> >
>> >
>> >>>> something
>> >>>>
>> >
>> >
>> >
>> >
>> >>> that
>> >>>
>> >
>> >
>> >
>> >
>> >>>> has to be learned. As more training materials come out on power
>> >>>>
>> >
>> >
>> >
>> >
>> >>> delivery,
>> >>>
>> >
>> >
>> >
>> >
>> >>>> it will probably get easier. In the shameless plug department, we (
>> >>>>
>> >
>> >
>> >>>> Teraspeed ) do very nice jobs optimizing power delivery systems for
>> >>>>
>> >
>> >
>> >>>> customers. If you've got a design you want advice on we can get you
>> >>>>
>> >
>> >
>> >>>> squared-up pretty quickly.
>> >>>>
>> >
>> >
>> >
>> >
>> >>>> Best Regards,
>> >>>>
>> >
>> >
>> >
>> >
>> >
>> >
>> >>>> Steve.
>> >>>>
>> >
>> >
>> >>>> Joel Brown wrote:
>> >>>>
>> >
>> >
>> >
>> >
>> >
>> >
>> >>>>> Steve,
>> >>>>>
>> >
>> >
>> >
>> >
>> >>>>> So even though each cap has a relatively high ESR (1.6 Ohms) the
>> >>>>>
>> >
>> >
>> >>>>> PDN as a whole has a relatively low impedance which will result in
>> >>>>>
>> >
>> >
>> >>>>> low noise on the PDN. This goes against intuition and previous
>> >>>>>
>> >
>> >
>> >>>>> thinking that an IC needs a local bypass with low ESR and ESL to
>> >>>>>
>> >
>> >
>> >>>>> supply the needed charge during switching transients. I am starting
>> >>>>>
>> >
>> >
>> >>>>> to see that mathematically a resistive PDN lowers noise compared to
>> >>>>>
>> >
>> >
>> >>>>> one that is the inductive (you did a good job explaining that). The
>> >>>>>
>> >
>> >
>> >>>>> thing that I am having trouble grasping or
>> >>>>>
>> >
>> >
>> >
>> >
>> >
>> >
>> >>>> visualizing
>> >>>>
>> >
>> >
>> >
>> >
>> >
>> >
>> >>>>> is that why is charge propagation velocity not a factor when the
>> >>>>>
>> >
>> >
>> >>>>> PDN is purely resistive? Is the PDN model simply a resistor in
>> >>>>>
>> >
>> >
>> >>>>> series with the
>> >>>>>
>> >
>> >
>> >
>> >
>> >
>> >
>> >>>> load
>> >>>>
>> >
>> >
>> >
>> >
>> >
>> >
>> >>>>> and distance has no effect? Perhaps there is an analogy that would
>> >>>>>
>> >
>> >
>> >>>>> make
>> >>>>>
>> >
>> >
>> >
>> >
>> >
>> >
>> >>>> this
>> >>>>
>> >
>> >
>> >
>> >
>> >
>> >
>> >>>>> concept easier to understand? Also, when I see app notes from IC
>> >>>>>
>> >
>> >
>> >>>>> vendors that recommend using a 0.1uF and 1000pF cap on each supply
>> >>>>>
>> >
>> >
>> >>>>> pin and then instead I use distributed high ESR capacitors I feel
>> >>>>>
>> >
>> >
>> >>>>> like I am doing something quite different and contrary from the
>> >>>>>
>> >
>> >
>> >>>>> recommended and when I
>> >>>>>
>> >
>> >
>> >
>> >
>> >
>> >
>> >>>> query
>> >>>>
>> >
>> >
>> >
>> >
>> >
>> >
>> >>>>> the vendors on how they arrived at recommendations in the app note
>> >>>>>
>> >
>> >
>> >>>>> the answer I get is "we recommend that you do it exactly as shown
>> >>>>>
>> >
>> >
>> >>>>> in the app note, we know it works that way and if you don't follow
>> >>>>>
>> >
>> >
>> >>>>> it it may not
>> >>>>>
>> >
>> >
>> >
>> >
>> >
>> >
>> >>>> work".
>> >>>>
>> >
>> >
>> >
>> >
>> >
>> >
>> >>>>> Also I am wondering how all this relates to X2Y caps, I suppose
>> >>>>>
>> >
>> >
>> >>>>> they could be used with series resistors but that would somewhat
>> >>>>>
>> >
>> >
>> >>>>> defeat the purpose
>> >>>>>
>> >
>> >
>> >
>> >
>> >
>> >
>> >>>> by
>> >>>>
>> >
>> >
>> >
>> >
>> >
>> >
>> >>>>> adding inductance. Its not clear to me what approaches I should
>> >>>>>
>> >
>> >
>> >>>>> attempt on future designs.
>> >>>>>
>> >
>> >
>> >
>> >
>> >>>>> Joel
>> >>>>>
>> >
>> >
>> >
>> >
>> >
>> >
>> >>>>> -----Original Message-----
>> >>>>>
>> >
>> >
>> >>>>> From: si-list-bounce@xxxxxxxxxxxxx
>> >>>>>
>> >
>> >
>> >>>>> [mailto:si-list-bounce@xxxxxxxxxxxxx]
>> >>>>>
>> >
>> >
>> >
>> >
>> >
>> >
>> >>>> On
>> >>>>
>> >
>> >
>> >
>> >
>> >
>> >
>> >>>>> Behalf Of steve weir
>> >>>>>
>> >
>> >
>> >>>>> Sent: Wednesday, March 12, 2008 11:26 PM
>> >>>>>
>> >
>> >
>> >>>>> To: Doug Brooks
>> >>>>>
>> >
>> >
>> >>>>> Cc: Istvan Novak; si-list@xxxxxxxxxxxxx
>> >>>>>
>> >
>> >
>> >>>>> Subject: [SI-LIST] Re: Antwort: Re: Questions about interplane
>> >>>>>
>> >
>> >
>> >>>>> capacitance
>> >>>>>
>> >
>> >
>> >
>> >
>> >>>>> Doug, Istvan's representations are analytically exact. When the
>> >>>>>
>> >
>> >
>> >>>>> characteristic impedance of the transmission structure is high,
>> >>>>>
>> >
>> >
>> >>>>> and/or the rise times are slow then capacitors can be placed in
>> >>>>>
>> >
>> >
>> >>>>> close enough
>> >>>>>
>> >
>> >
>> >
>> >
>> >
>> >
>> >>>> proximity
>> >>>>
>> >
>> >
>> >
>> >
>> >
>> >
>> >>>>> that they load the transmission structure so as to make it appear a
>> >>>>>
>> >
>> >
>> >>>>> lower impedance with some little bumps. For example if one had a 10"
>> >>>>>
>> >
>> >
>> >>>>> x 10" 4
>> >>>>>
>> >
>> >
>> >
>> >
>> >
>> >
>> >>>> mil
>> >>>>
>> >
>> >
>> >
>> >
>> >
>> >
>> >>>>> er4.0 board =3D 22.5nF and loaded it with bypass every square inch of
>> >>>>>
>> >
>> >
>> >>>>> 150pH, then for slow enough signals, the distributed impedance
>> >>>>>
>> >
>> >
>> >>>>> would look like 80mOhms. If the network were constructed from 200
>> >>>>>
>> >
>> >
>> >>>>> capacitors, an ESR
>> >>>>>
>> >
>> >
>> >
>> >
>> >
>> >
>> >>>> value
>> >>>>
>> >
>> >
>> >
>> >
>> >
>> >
>> >>>>> of 1.6Ohms / cap would make that impedance uniform down to the RC
>> >>>>>
>> >
>> >
>> >>>>> knee of the parts. Assume that were matched by an AVP regulator of
>> >>>>>
>> >
>> >
>> >>>>> 80mOhms and
>> >>>>>
>> >
>> >
>> >
>> >
>> >
>> >
>> >>>> the
>> >>>>
>> >
>> >
>> >
>> >
>> >
>> >
>> >>>>> entire thing looks like 80mOhms from DC to over 1GHz. 80mOhms
>> >>>>>
>> >
>> >
>> >>>>> would
>> >>>>>
>> >
>> >
>> >
>> >
>> >
>> >
>> >>>> support
>> >>>>
>> >
>> >
>> >
>> >
>> >
>> >
>> >>>>> a 32 bit transition w/ about 5% droop. The impedance scales with
>> >>>>>
>> >
>> >
>> >
>> >
>> >
>> >
>> >>>> dielectric
>> >>>>
>> >
>> >
>> >
>> >
>> >
>> >
>> >>>>> height and the inverse square root of eR. Scale the dielectric
>> >>>>>
>> >
>> >
>> >>>>> down to 0.1mils and now 320 lines can switch simultaneously in one
>> >>>>>
>> >
>> >
>> >>>>> direction with
>> >>>>>
>> >
>> >
>> >
>> >
>> >
>> >
>> >>>> 5%
>> >>>>
>> >
>> >
>> >
>> >
>> >
>> >
>> >>>>> droop, and at arbitrary edge rates.
>> >>>>>
>> >
>> >
>> >
>> >
>> >>>>> Istvan has shown using analysis with the reverse pulse technique an
>> >>>>>
>> >
>> >
>> >>>>> inductive PDN shunt impedance acts like a noise high pass filter (
>> >>>>>
>> >
>> >
>> >>>>> See DC papers from at least as far back as DC East 2005 ). Put in
>> >>>>>
>> >
>> >
>> >>>>> a square wave noise pulse ( load current ) and the leading edge
>> >>>>>
>> >
>> >
>> >>>>> changes by Vdelta =3D -L*di/dt below the baseline. Allow the pulse
>> >>>>>
>> >
>> >
>> >>>>> to persist long enough and
>> >>>>>
>> >
>> >
>> >
>> >
>> >
>> >
>> >>>> the
>> >>>>
>> >
>> >
>> >
>> >
>> >
>> >
>> >>>>> system recovers back to the baseline which would be -I*Rpdn.
>> >>>>>
>> >
>> >
>> >>>>> Return the load current to zero, and now the energy stored in the
>> >>>>>
>> >
>> >
>> >
>> >
>> >
>> >
>> >>>> inductance
>> >>>>
>> >
>> >
>> >
>> >
>> >
>> >
>> >>>>> kicks back -L*di/dt. The p-p noise is then 2*Ldi/dt - (Imax-
>> >>>>>
>> >
>> >
>> >
>> >
>> >>> Imin)*Rpdn.
>> >>>
>> >
>> >
>> >
>> >
>> >>>> If
>> >>>>
>> >
>> >
>> >
>> >
>> >
>> >
>> >>>>> Rpdn is very small then it approximates 2*Ldi/dt.
>> >>>>>
>> >
>> >
>> >>>>> This behavior is apparent in the transient response plots of
>> >>>>>
>> >
>> >
>> >>>>> virtually any non-AVP VRM.
>> >>>>>
>> >
>> >
>> >
>> >
>> >>>>> Now, suppose that the VRM and PDN can be made to appear resistive
>> >>>>>
>> >
>> >
>> >>>>> right through Fknee. Then the response to a current pulse of I is
>> >>>>>
>> >
>> >
>> >>>>> simply Vdelta
>> >>>>>
>> >
>> >
>> >
>> >
>> >
>> >
>> >>>> =3D
>> >>>>
>> >
>> >
>> >
>> >
>> >
>> >
>> >>>>> -I*Rpdn. There is no component of di/dt, and so the total p-p
>> >>>>>
>> >
>> >
>> >>>>> noise is
>> >>>>>
>> >
>> >
>> >
>> >
>> >
>> >
>> >>>> just
>> >>>>
>> >
>> >
>> >
>> >
>> >
>> >
>> >>>>> (Imax - Imin)*Rpdn. AVP schemes position the DC operating point
>> >>>>>
>> >
>> >
>> >>>>> intentionally high so that at Imin they are at their margined high
>> >>>>>
>> >
>> >
>> >>>>> limits and at Imax they are at their low limits. This allows
>> >>>>>
>> >
>> >
>> >>>>> increasing Rpdn
>> >>>>>
>> >
>> >
>> >
>> >
>> >
>> >
>> >>>> while
>> >>>>
>> >
>> >
>> >
>> >
>> >
>> >
>> >>>>> still meeting the same current and voltage specifications.
>> >>>>>
>> >
>> >
>> >
>> >
>> >>>>> Best Regards,
>> >>>>>
>> >
>> >
>> >
>> >
>> >
>> >
>> >>>>> Steve.
>> >>>>>
>> >
>> >
>> >
>> >
>> >
>> >
>> >>>>> Doug Brooks wrote:
>> >>>>>
>> >
>> >
>> >
>> >
>> >
>> >
>> >
>> >
>> >>>>>> Istvan,
>> >>>>>>
>> >
>> >
>> >
>> >
>> >>>>>> With all due respect, I would modify your argument a little bit.
>> >>>>>>
>> >
>> >
>> >>>>>> In very simplistic terms, suppose we need x amount of charge to
>> >>>>>>
>> >
>> >
>> >>>>>> transition from a zero to a one in one ns. That amount of charge
>> >>>>>>
>> >
>> >
>> >>>>>> (I
>> >>>>>>
>> >
>> >
>> >>>>>> suggest) must be within
>> >>>>>>
>> >
>> >
>> >>>>>> 6 inches of the need (what I think we are referring to as the
>> >>>>>>
>> >
>> >
>> >>>>>> service radius). If not, it takes a little longer to reach the
>> >>>>>>
>> >
>> >
>> >>>>>> logical one
>> >>>>>>
>> >
>> >
>> >
>> >
>> >>> state.
>> >>>
>> >
>> >
>> >
>> >
>> >>>>>> I look at it, not from the standpoint of a dip in the rail, as
>> >>>>>>
>> >
>> >
>> >>>>>> much as the ability to satisfy the rise time requirement (unless
>> >>>>>>
>> >
>> >
>> >>>>>> you are referring to a dip in the rail that occurs during the rise
>> >>>>>>
>> >
>> >
>> >>>>>> time
>> >>>>>>
>> >
>> >
>> >>>>>> itself.) In the slightly longer term, the charge will replenish
>> >>>>>>
>> >
>> >
>> >>>>>> fairly quickly, but not, perhaps fast enough to meet the rise time
>> >>>>>>
>> >
>> >
>> >
>> >
>> >
>> >
>> >>>> requirement.
>> >>>>
>> >
>> >
>> >
>> >
>> >
>> >
>> >>>>>> Doug Brooks
>> >>>>>>
>> >>>>>>
>>
>>
>> ------------------------------------------------------------------
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>>
>> or to administer your membership from a web page, go to:
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>>
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>>
>>
>> List technical documents are available at:
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>>
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>> or at our remote archives:
>> http://groups.yahoo.com/group/si-list/messages
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>>
>>
>>
>>
>
>
>
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Old (prior to June 6, 2001) list archives are viewable at:
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