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[SI-LIST] Re: Questions about interplane capacitance
- From: "Jennings, Kevin F" <Kevin.Jennings@xxxxxxxxxx>
- To: "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
- Date: Fri, 14 Mar 2008 14:15:25 -0500
Istvan,
For the garden variety PCB material Er ~4, a 1 inch by 1 inch square will h=
ave C ~ 1nF per mil thickness and L ~32pH per mil thickness (both Dr. Eric =
B's approximations) giving the following characteristic impedances as a fun=
ction of dielectric thickness
H(mils) Z(ohms)
------ ----
1 0.18
2 0.36
3 0.54
4 0.72
5 0.89
Assuming you need to keep voltage regulation to within 5%, then the maximum=
amount of current you'll be able to draw as a function of dielectric thick=
ness will be .05 / Z
H Z dI(Amps)
-- ---- --------
1 0.18 0.280
2 0.36 0.140
3 0.54 0.093
4 0.72 0.070
5 0.89 0.056
Or did I miss something entirely?
Interesting technique even if it might only be applicable for relatively lo=
w power situations.
Kevin Jennings
> Date: Fri, 14 Mar 2008 08:57:57 -0400
> From: Istvan Novak <istvan.novak@xxxxxxxxxxx>
> Subject: [SI-LIST] Re: Antwort: Re: Questions about interplane
> capacitance
>
> Joel,
>
> Imagine the following. You establish your impedance target. For sake
> of simplicity lets assume you have a single load (a single pin) to
> feed with clean power.
> We know from
> previous analysis that minimizing the worst-case transient
> peak-to-peak noise can be done by setting the impedance target to be
> flat within the frequency range of interest.
> For sake of simplicity lets assume the frequency range of interest is
> from DC to Fmax.
> On a circuit schematics your ideal PDN solution is a series R-L source
> impedance, where R is your impedance target, and L is such that
> Fmax=3D1/(2*PI*L/R).
> If the
> PDN design is done properly, the load-current fluctuations will create
> only acceptably small voltage noise on the supply rail, in other words
> the load impedance is much greater than R, so your source operates in
> the 'unloaded' mode.
>
> To turn the ideal schematics into an actual circuit, you can choose
> from a large number of methods to synthesize the source impedance.
> One attractive option is to take a transmission line of characteristic
> impedance of R, match it at both ends, and to connect one end to the
> DC source, the other end to your load. The required PDN impedance
> (R) is usually
> way lower than 50 ohms, so this is not your typical coax cable or
> signal trace, but the physics is the same regardless of the
> characteristic impedance: a terminated transmission line shows its
> characteristic impedance regardless of its length and frequency. For
> PDN analysis, the characteristic impedance can be considered constant
> even if we have losses and dispersion. The transmission line is a
> distributed R-L-G-C network, where even if we neglect R and G, the
> signal propagates through the series of capacitive and inductive
> contributors. The approximate characteristic impedance is sqrt(L/C)
> and the approximate propagation delay is sqrt(L*C). If you take this
> terminated transmission line, it will show
> R/2 impedance at the load point, regardless of its length and delay.
> If the load current fluctuates (within the bandwidth of Fmax), the
> voltage fluctuation will be R/2*I(t).
> (note: when you consider a one-dimensional transmission line, matched
> at both ends, your actual impedance shown to the load is R/2, unless
> you use source termination only, which gives you an impedance of R).
>
> In the above circuit, the charge flows continuously from source to
> load, and delay does not matter.
>
> The key to the above simplistic picture is the matching: if we
> consider bypass capacitors, those must have resistances properly
> matching the plane structure's characteristic impedance.
> I call them Bypass Resistors, because it is really their resistance
> what
> matters: C and L
> are less important. C is there only to make sure we do not draw DC
> current with the termination (so it should be as high value as
> possible), and L is there as physical reality, so it should be as low
> as conveniently possible.
>
> Regards,
>
> Istvan Novak
> SUN Microsystems
>
>
> Joel Brown wrote:
> > I hate to prolong this but...
> > When I think about a transmission line in the normal sense (signal
> > propagation), A driver switches at one end but initially all it sees
> > is
> Zo
> > which looks like a resistor maybe 50 ohms and it does not even see
> > the
> load
> > until wave propagates the length of the line. So there is a time delay.
> Now
> > think of the driver being the power pin of the IC and the load being
> > the bypass cap on the corner of the board or visa versa and I see a
> propagation
> > delay, so what am I missing?
> >
> > Joel
> >
> >
> > -----Original Message-----
> > From: SILR [mailto:silr@xxxxxxxxxxxx]
> > Sent: Thursday, March 13, 2008 6:27 PM
> > To: 'steve weir'; 'Joel Brown'
> > Cc: 'Istvan Novak'; si-list@xxxxxxxxxxxxx
> > Subject: RE: [SI-LIST] Re: Antwort: Re: Questions about interplane
> > capacitance
> >
> > Joel asked:
> > <<< ...why is charge propagation velocity not a factor when the PDN
> > is purely resistive? >>>
> >
> >
> > Well, here's a crazy way to think about this (which I'm sure not
> everyone
> > will agree)... I guess this would be like how Eric B. might put it...
> "Be
> > the Signal"
> >
> >
> > I'm the charge on some corner of a board...there's an IC in the
> > middle
> of
> > the board...
> >
> > I have to get to that IC using this transmission line called the PDN.
> If
> > this Transmission Line had the classical Ls and Cs (and Rs) to
> > describe
> its
> > characteristics, then that means I have to deal with changing EM
> > fields
> to
> > get to that IC... but these time varying EM fields always cause
> > some
> delay
> > in my charge getting to that IC in a timely manner...
> >
> > BUT!!! ...if this Transmission Line had nothing but Rs (no Ls and
> > Cs) to describe its characteristics then that means I don't have to
> > deal with
> time
> > varying EM fields any longer... I just have to deal with resistive
> losses
> > only but this only equates to a drop in Static Voltage Potential and
> nothing
> > more... (so keep the Z low!!!) And I can get there (to the IC) in
> > no
> time
> > and the IC gets the charges that it needs and it wouldn't even know
> anything
> > is different...
> >
> > Again, this is a crazy way to look at this... but it works for me, for
> > now... until I get grilled by the senior members... :-)
> >
> > Silvester
> >
> > -----Original Message-----
> > From: si-list-bounce@xxxxxxxxxxxxx
> > [mailto:si-list-bounce@xxxxxxxxxxxxx]
> On
> > Behalf Of steve weir
> > Sent: Thursday, March 13, 2008 5:57 PM
> > To: Joel Brown
> > Cc: 'Istvan Novak'; si-list@xxxxxxxxxxxxx
> > Subject: [SI-LIST] Re: Antwort: Re: Questions about interplane
> capacitance
> >
> > Joel, it is transmission line theory. Think about an infinitely
> > long signal transmission line for a moment. At any instant a driver
> > sees a constant impedance across frequency. The voltage to current
> > relation is independent of prior history. What Istvan describes is
> > a very low
> impedance
> > transmission structure for power.
> >
> > Sadly, a lot of IC vendors are still playing catch-up in terms of
> > power delivery. If they had their game together, they would be telling=
you:
> > The actual voltage tolerances at the die, the current spectrum at
> > the
> die,
> > and the parasitics of the die and package. From that you could
> > engineer your PDN. Instead often what we see are partial recipes
> > like you
> describe.
> > On a good day the recipes cost extra money. On a bad day, they
> > result
> in
> > failures.
> >
> > One can build a resistive networks several ways. One is to add
> > discrete resistance by any number of methods, another is to use the
> > FDTIM method
> that
> > Larry Smith has long championed. And even though resistive networks
> have
> > attractive qualities, reactive networks may still be cheaper and
> > equally effective. It all depends on the circumstances. It is
> > somewhat akin to surface finishes: there is no ideal one. But
> > there are several that
> when
> > used properly work very well. One just needs to respect the
> > limitations
> of
> > each method.
> >
> > Part of the problem figuring this stuff out is having sufficient
> experience
> > to judge trade-offs early in the design process. That's just
> > something
> that
> > has to be learned. As more training materials come out on power
> delivery,
> > it will probably get easier. In the shameless plug department, we (
> > Teraspeed ) do very nice jobs optimizing power delivery systems for
> > customers. If you've got a design you want advice on we can get you
> > squared-up pretty quickly.
> >
> > Best Regards,
> >
> >
> > Steve.
> > Joel Brown wrote:
> >
> >> Steve,
> >>
> >> So even though each cap has a relatively high ESR (1.6 Ohms) the
> >> PDN as a whole has a relatively low impedance which will result in
> >> low noise on the PDN. This goes against intuition and previous
> >> thinking that an IC needs a local bypass with low ESR and ESL to
> >> supply the needed charge during switching transients. I am starting
> >> to see that mathematically a resistive PDN lowers noise compared to
> >> one that is the inductive (you did a good job explaining that). The
> >> thing that I am having trouble grasping or
> >>
> > visualizing
> >
> >> is that why is charge propagation velocity not a factor when the
> >> PDN is purely resistive? Is the PDN model simply a resistor in
> >> series with the
> >>
> > load
> >
> >> and distance has no effect? Perhaps there is an analogy that would
> >> make
> >>
> > this
> >
> >> concept easier to understand? Also, when I see app notes from IC
> >> vendors that recommend using a 0.1uF and 1000pF cap on each supply
> >> pin and then instead I use distributed high ESR capacitors I feel
> >> like I am doing something quite different and contrary from the
> >> recommended and when I
> >>
> > query
> >
> >> the vendors on how they arrived at recommendations in the app note
> >> the answer I get is "we recommend that you do it exactly as shown
> >> in the app note, we know it works that way and if you don't follow
> >> it it may not
> >>
> > work".
> >
> >> Also I am wondering how all this relates to X2Y caps, I suppose
> >> they could be used with series resistors but that would somewhat
> >> defeat the purpose
> >>
> > by
> >
> >> adding inductance. Its not clear to me what approaches I should
> >> attempt on future designs.
> >>
> >> Joel
> >>
> >>
> >> -----Original Message-----
> >> From: si-list-bounce@xxxxxxxxxxxxx
> >> [mailto:si-list-bounce@xxxxxxxxxxxxx]
> >>
> > On
> >
> >> Behalf Of steve weir
> >> Sent: Wednesday, March 12, 2008 11:26 PM
> >> To: Doug Brooks
> >> Cc: Istvan Novak; si-list@xxxxxxxxxxxxx
> >> Subject: [SI-LIST] Re: Antwort: Re: Questions about interplane
> >> capacitance
> >>
> >> Doug, Istvan's representations are analytically exact. When the
> >> characteristic impedance of the transmission structure is high,
> >> and/or the rise times are slow then capacitors can be placed in
> >> close enough
> >>
> > proximity
> >
> >> that they load the transmission structure so as to make it appear a
> >> lower impedance with some little bumps. For example if one had a 10"
> >> x 10" 4
> >>
> > mil
> >
> >> er4.0 board =3D 22.5nF and loaded it with bypass every square inch of
> >> 150pH, then for slow enough signals, the distributed impedance
> >> would look like 80mOhms. If the network were constructed from 200
> >> capacitors, an ESR
> >>
> > value
> >
> >> of 1.6Ohms / cap would make that impedance uniform down to the RC
> >> knee of the parts. Assume that were matched by an AVP regulator of
> >> 80mOhms and
> >>
> > the
> >
> >> entire thing looks like 80mOhms from DC to over 1GHz. 80mOhms
> >> would
> >>
> > support
> >
> >> a 32 bit transition w/ about 5% droop. The impedance scales with
> >>
> > dielectric
> >
> >> height and the inverse square root of eR. Scale the dielectric
> >> down to 0.1mils and now 320 lines can switch simultaneously in one
> >> direction with
> >>
> > 5%
> >
> >> droop, and at arbitrary edge rates.
> >>
> >> Istvan has shown using analysis with the reverse pulse technique an
> >> inductive PDN shunt impedance acts like a noise high pass filter (
> >> See DC papers from at least as far back as DC East 2005 ). Put in
> >> a square wave noise pulse ( load current ) and the leading edge
> >> changes by Vdelta =3D -L*di/dt below the baseline. Allow the pulse
> >> to persist long enough and
> >>
> > the
> >
> >> system recovers back to the baseline which would be -I*Rpdn.
> >> Return the load current to zero, and now the energy stored in the
> >>
> > inductance
> >
> >> kicks back -L*di/dt. The p-p noise is then 2*Ldi/dt - (Imax-
> Imin)*Rpdn.
> >>
> > If
> >
> >> Rpdn is very small then it approximates 2*Ldi/dt.
> >> This behavior is apparent in the transient response plots of
> >> virtually any non-AVP VRM.
> >>
> >> Now, suppose that the VRM and PDN can be made to appear resistive
> >> right through Fknee. Then the response to a current pulse of I is
> >> simply Vdelta
> >>
> > =3D
> >
> >> -I*Rpdn. There is no component of di/dt, and so the total p-p
> >> noise is
> >>
> > just
> >
> >> (Imax - Imin)*Rpdn. AVP schemes position the DC operating point
> >> intentionally high so that at Imin they are at their margined high
> >> limits and at Imax they are at their low limits. This allows
> >> increasing Rpdn
> >>
> > while
> >
> >> still meeting the same current and voltage specifications.
> >>
> >> Best Regards,
> >>
> >>
> >> Steve.
> >>
> >>
> >> Doug Brooks wrote:
> >>
> >>
> >>> Istvan,
> >>>
> >>> With all due respect, I would modify your argument a little bit.
> >>> In very simplistic terms, suppose we need x amount of charge to
> >>> transition from a zero to a one in one ns. That amount of charge
> >>> (I
> >>> suggest) must be within
> >>> 6 inches of the need (what I think we are referring to as the
> >>> service radius). If not, it takes a little longer to reach the
> >>> logical one
> state.
> >>> I look at it, not from the standpoint of a dip in the rail, as
> >>> much as the ability to satisfy the rise time requirement (unless
> >>> you are referring to a dip in the rail that occurs during the rise
> >>> time
> >>> itself.) In the slightly longer term, the charge will replenish
> >>> fairly quickly, but not, perhaps fast enough to meet the rise time
> >>>
> > requirement.
> >
> >>> Doug Brooks
> >>>
> >>>
> >>>
> >>>
> >>>
> >>>
> >>>> Andreas,
> >>>>
> >>>> Yes and no. It is true that charge moves with finite speed, so
> >>>> for any given time duration the charge has to come from locations
> >>>> closer than the ratio of distance over speed. BUT the whole
> >>>> notion of service radius is based on the assumption that as you
> >>>> deplete the charge available in the immediate vicinity of the
> >>>> active device, you have to wait for replenishment, otherwise you
> >>>> get a big dip on the supply rail.
> >>>>
> >>>> Having a matched
> >>>> transmission medium to deliver power to the active device, the
> >>>> charge moves without interruption, and as you deplete the planes
> >>>> close to the device, it gets replenished on the fly from areas
> >>>> further away, so the service area concept is pretty much
> >>>> meaningless in this scenario. Current flows without interruption.
> >>>> The bucket brigade of infinitesimally small inductive and
> >>>> capacitive elements of the transmission line transmits the power con=
tinuously.
> >>>> If the load current changes, for any I(t) time function of load
> >>>> current, the transient noise at the load point will be I(t)*Zo,
> >>>> where we assume that Zo is the resistive and frequency
> >>>> independent characteristic impedance of the transmission medium.
> >>>> This is a very simplistic one-dimensional model, but it gives a
> >>>> good insight of why the service radius matters only on PDNs where
> >>>> the network is not matched.
> >>>>
> >>>> Regards,
> >>>>
> >>>> Istvan Novak
> >>>> SUN Microsystems
> >>>>
> >>>>
> >>>>
> >>>>
> >>>>
> >>>> Andreas.Lenkisch@xxxxxxxxxx wrote:
> >>>>
> >>>>
> >>>>
> >>>>> Istvan,
> >>>>> I'm wodering a little about your comments to the service radius.
> >>>>> Independant if the impedance is resistive, we have still a
> >>>>> propagation time which would limit the service radius from my
> >>>>>
> >>>>>
> >> understanding.
> >>
> >>
> >>>>> Do I'm wrong?
> >>>>>
> >>>>> regards
> >>>>> Andreas
> >>>>>
> >>>>>
> >>>>>
> >>>>> Istvan Novak <istvan.novak@xxxxxxxxxxx> Gesendet von:
> >>>>> si-list-bounce@xxxxxxxxxxxxx
> >>>>> 11.03.2008 13:14
> >>>>>
> >>>>> An
> >>>>> Joel Brown <joel@xxxxxxxxxx>
> >>>>> Kopie
> >>>>> si-list@xxxxxxxxxxxxx
> >>>>> Thema
> >>>>> [SI-LIST] Re: Questions about interplane capacitance
> >>>>>
> >>>>>
> >>>>>
> >>>>>
> >>>>>
> >>>>>
> >>>>> Joel,
> >>>>>
> >>>>> Just one quick comments to the good summary from Steve:
> >>>>>
> >>>>> While considering planes and bypass capacitors in terms of
> >>>>> effective capacitances and inductances is a valid approach, we
> >>>>> need to keep in mind that focusing on the capacitive or
> >>>>> inductive nature of parts without looking at the wider picture
> >>>>> misses a very important and useful class of solutions, namely
> >>>>> that of matched transmission lines. As it was pointed out
> >>>>> earlier several times on the SI list, the best
> >>>>> (self) impedance for a power distribution network is a resistive
> >>>>> one, neither capacitive, nor inductive.
> >>>>> We can get resistive impedance from a matched transmission line,
> >>>>> regardless of its capacitance and inductance, and in such cases
> >>>>> the notion of 'service area' of parts become meaningless: you
> >>>>> can put bypass components further away from the active devices
> >>>>> without sacrificing performance.
> >>>>>
> >>>>> Regards,
> >>>>>
> >>>>> Istvan Novak
> >>>>> SUN Microsystems
> >>>>>
> >>>>> Joel Brown wrote:
> >>>>>
> >>>>>
> >>>>>
> >>>>>
> >>>>>> Interplane capacitance is frequently cited as the only
> >>>>>> effective bypass capacitance on a PCB at frequencies above 200 MHz=
.
> >>>>>> I am currently working on a design which brings up some
> >>>>>> questions
> >>>>>>
> >>>>>>
> >>>>>>
> >>>>>>
> >>>>> regarding
> >>>>>
> >>>>>
> >>>>>
> >>>>>
> >>>>>> interplane capacitance.
> >>>>>>
> >>>>>> 1. Power planes normally carry "standard" voltage rails that
> >>>>>> are used throughout a board such as +5V and +3.3V.
> >>>>>> High speed ICs usually have core voltages that are local to the
> >>>>>> IC and
> >>>>>>
> >>>>>>
> >>>>>>
> >>>>>>
> >>>>> are
> >>>>>
> >>>>>
> >>>>>
> >>>>>
> >>>>>> provided by a local regulator which converts the standard rail
> >>>>>> to the
> >>>>>>
> >>>>>>
> >>>>>>
> >>>>>>
> >>>>> core
> >>>>>
> >>>>>
> >>>>>
> >>>>>
> >>>>>> voltage (example 3.3 to 1.8V).
> >>>>>> The local core voltage is distributed on a plane area that is
> >>>>>> local to
> >>>>>>
> >>>>>>
> >>>>>>
> >>>>>>
> >>>>> the
> >>>>>
> >>>>>
> >>>>>
> >>>>>
> >>>>>> IC and therefore is small in area (0.25 sq in or less) which
> >>>>>> results in
> >>>>>>
> >>>>>>
> >>>>>>
> >>>>>>
> >>>>> a
> >>>>>
> >>>>>
> >>>>>
> >>>>>
> >>>>>> very small amount of interplane capacitance.
> >>>>>> Is this very small amount of capicitance effective for
> >>>>>> bypassing the IC?
> >>>>>>
> >>>>>>
> >>>>>>
> >>>>>>
> >>>>> I
> >>>>>
> >>>>>
> >>>>>
> >>>>>
> >>>>>> am sure it depends somewhat on the current waveform being drawn
> >>>>>> by the
> >>>>>>
> >>>>>>
> >>>>>>
> >>>>>>
> >>>>> IC
> >>>>>
> >>>>>
> >>>>>
> >>>>>
> >>>>>> but this can only be estimated because semiconductor
> >>>>>> manufacturers do
> >>>>>>
> >>>>>>
> >>>>>>
> >>>>>>
> >>>>> not
> >>>>>
> >>>>>
> >>>>>
> >>>>>
> >>>>>> provide current consumption profile as a function of frequency.
> >>>>>> To make matters worse, some ICs have several different VCC pins
> >>>>>> which the manufacturer recommends connecting to separate
> >>>>>> networks of bypass caps
> >>>>>>
> >>>>>>
> >>>>>>
> >>>>>>
> >>>>> and
> >>>>>
> >>>>>
> >>>>>
> >>>>>
> >>>>>> ferrite beads. This cuts the power distributuion up even more
> >>>>>> resulting
> >>>>>>
> >>>>>>
> >>>>>>
> >>>>>>
> >>>>> in
> >>>>>
> >>>>>
> >>>>>
> >>>>>
> >>>>>> less (practically zero) interplane capacitance. It is somewhat
> >>>>>> ironic
> >>>>>>
> >>>>>>
> >>>>>>
> >>>>>>
> >>>>> that
> >>>>>
> >>>>>
> >>>>>
> >>>>>
> >>>>>> the the voltages such as +5V and +3.3V which are required at
> >>>>>> points
> >>>>>>
> >>>>>>
> >>>>>>
> >>>>>>
> >>>>> across
> >>>>>
> >>>>>
> >>>>>
> >>>>>
> >>>>>> the whole board and therefore have the most interplane
> >>>>>> capacitance are
> >>>>>>
> >>>>>>
> >>>>>>
> >>>>>>
> >>>>> also
> >>>>>
> >>>>>
> >>>>>
> >>>>>
> >>>>>> the voltages which have least requirement for interplane
> >>>>>> capacitance
> >>>>>>
> >>>>>>
> >>>>>>
> >>>>>>
> >>>>> because
> >>>>>
> >>>>>
> >>>>>
> >>>>>
> >>>>>> they do not directly supply high speed rails.
> >>>>>>
> >>>>>> 2. There has been a lot of emphasis on reducing the mounted
> >>>>>> inductance
> >>>>>>
> >>>>>>
> >>>>>>
> >>>>>>
> >>>>> of
> >>>>>
> >>>>>
> >>>>>
> >>>>>
> >>>>>> bypass capacitors. Even with this reduced inductance they are
> >>>>>> still only effective up to several hundereds of MHz at which
> >>>>>> point the interplane capacitance becomes the only bypass
> >>>>>> capacitance mechanism. However there
> >>>>>>
> >>>>>>
> >>>>>>
> >>>>>>
> >>>>> is
> >>>>>
> >>>>>
> >>>>>
> >>>>>
> >>>>>> inductance between the connection of the IC to the planes. This
> >>>>>>
> >>>>>>
> >>>>>>
> >>>>>>
> >>>>> inductance
> >>>>>
> >>>>>
> >>>>>
> >>>>>
> >>>>>> consists of vias and package inductance. I did look for some
> >>>>>> numbers for package inductance and did not find much, it seems
> >>>>>> to be a closely held secret. Also it is unknown how much bypass
> >>>>>> capacitnace is internal to
> >>>>>>
> >>>>>>
> >>>>>>
> >>>>>>
> >>>>> the IC
> >>>>>
> >>>>>
> >>>>>
> >>>>>
> >>>>>> package. Just for example if we assume 250pH for the vias and
> >>>>>> 500 pH for
> >>>>>>
> >>>>>>
> >>>>>>
> >>>>>>
> >>>>> the
> >>>>>
> >>>>>
> >>>>>
> >>>>>
> >>>>>> package, then the impedance at 500 MHz would be 2.36 Ohms. This
> >>>>>> seems
> >>>>>>
> >>>>>>
> >>>>>>
> >>>>>>
> >>>>> rather
> >>>>>
> >>>>>
> >>>>>
> >>>>>
> >>>>>> high for the interplane capacitance to be of much benefit.
> >>>>>>
> >>>>>> In summary how much interplane capacitance is needed to be
> >>>>>> beneficial,
> >>>>>>
> >>>>>>
> >>>>>>
> >>>>>>
> >>>>> and
> >>>>>
> >>>>>
> >>>>>
> >>>>>
> >>>>>> why is it beneficial given the inductance in the vias and package?
> >>>>>>
> >>>>>> Thanks - Joel
> >>>>>>
> >>>>>>
> >>>>>>
> >>>>>>
> >>>>>>
> >>>>>>
> >>>>>>
> >>>>>>
>
>
>
> ------------------------------
>
> Msg: #3 in digest
> Date: Fri, 14 Mar 2008 09:14:54 -0400
> From: Istvan Novak <istvan.novak@xxxxxxxxxxx>
> Subject: [SI-LIST] Re: Questions about interplane capacitance; Reverse
> Pulse Te
>
> I got a few off-line questions asking about the Reverse Pulse
> Technique that Steve mentioned a couple of days ago on this thread.
>
> The original source is: Drabkin, et al, "Aperiodic Resonant Excitation
> of Microprocessor power Distribution Systems and the Reverse Pulse
> Technique," Proc. of EPEP 2002, p. 175.
>
> Note that an extended version of this classic paper will appear in the
> book: Power Distribution Network Design Methodologies, IEC, 2008,
> ISBN: 1-931695-65-2 (http://www.iec.org/pubs/pub.asp?pid=3D100&bsi=3D3).
>
> Regards,
>
> Istvan Novak
> SUN Microsystems
>
>
>
> ------------------------------
>
> Msg: #4 in digest
> From: "Joel Brown" <joel@xxxxxxxxxx>
> Subject: [SI-LIST] Re: Antwort: Re: Questions about interplane
> capacitance
> Date: Fri, 14 Mar 2008 09:08:27 -0700
>
> OK guys, I finally get it. What was getting in my way was the
> conventional thinking about charge transfer from a bypass cap to an IC
> and the inherent time delay of a transmission line. Then I started
> thinking again about how a signal propagates a trnsmission line and
> the light came on. Low PDN impedance implies high capacitance and
> charge storage, When the IC switches it sees Zo of the PDN at the
> immediate vicinity of the IC and this where the the charge comes from
> initially. As time goes by, the transient propagates the PDN and
> charge comes from further and further away but the delay does not
> matter because the IC is seeing constant charge delivery. Like
> Silvester said I am not sure if this is what actually happens but it
> satisfies my mind.
>
> Joel
>
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx
> [mailto:si-list-bounce@xxxxxxxxxxxxx]
> On
> Behalf Of Istvan Novak
> Sent: Friday, March 14, 2008 5:58 AM
> To: Joel Brown
> Cc: 'SILR'; 'steve weir'; si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: Antwort: Re: Questions about interplane
> capacitance
>
> Joel,
>
> Imagine the following. You establish your impedance target. For sake
> of simplicity lets assume you have a single load (a single pin) to
> feed with clean power.
> We know from
> previous analysis that minimizing the worst-case transient
> peak-to-peak noise can be done by setting the impedance target to be
> flat within the frequency range of interest.
> For sake of simplicity lets assume the frequency range of interest is
> from DC to Fmax.
> On a circuit schematics your ideal PDN solution is a series R-L source
> impedance, where R is your impedance target, and L is such that
> Fmax=3D1/(2*PI*L/R).
> If the
> PDN design is done properly, the load-current fluctuations will create
> only acceptably small voltage noise on the supply rail, in other words
> the load impedance is much greater than R, so your source operates in
> the 'unloaded'
> mode.
>
> To turn the ideal schematics into an actual circuit, you can choose
> from a large number of methods to synthesize the source impedance.
> One attractive option is to take a transmission line of characteristic
> impedance of R, match it at both ends, and to connect one end to the
> DC source, the other end to your load. The required PDN impedance
> (R) is usually
> way lower than 50 ohms, so this is not your typical coax cable or
> signal trace, but the physics is the same regardless of the
> characteristic
> impedance: a terminated transmission line shows its characteristic
> impedance regardless of its length and frequency. For PDN analysis,
> the characteristic impedance can be considered constant even if we
> have losses and dispersion. The transmission line is a distributed
> R-L-G-C network, where even if we neglect R and G, the signal
> propagates through the series of capacitive and inductive
> contributors. The approximate characteristic impedance is sqrt(L/C)
> and the approximate propagation delay is sqrt(L*C).
> If you take this terminated transmission line, it will show
> R/2 impedance at the load point, regardless of its length and delay.
> If the load current fluctuates (within the bandwidth of Fmax), the
> voltage fluctuation will be R/2*I(t).
> (note: when you consider a one-dimensional transmission line, matched
> at both ends, your actual impedance shown to the load is R/2, unless
> you use source termination only, which gives you an impedance of R).
>
> In the above circuit, the charge flows continuously from source to
> load, and delay does not matter.
>
> The key to the above simplistic picture is the matching: if we
> consider bypass capacitors, those must have resistances properly
> matching the plane structure's characteristic impedance.
> I call them Bypass Resistors, because it is really their resistance
> what
> matters: C and L
> are less important. C is there only to make sure we do not draw DC
> current with the termination (so it should be as high value as
> possible), and L is there as physical reality, so it should be as low
> as conveniently possible.
>
> Regards,
>
> Istvan Novak
> SUN Microsystems
>
>
> Joel Brown wrote:
> > I hate to prolong this but...
> > When I think about a transmission line in the normal sense (signal
> > propagation), A driver switches at one end but initially all it sees
> > is Zo which looks like a resistor maybe 50 ohms and it does not even
> > see the load until wave propagates the length of the line. So there
> > is a time delay. Now think of the driver being the power pin of the
> > IC and the load being the bypass cap on the corner of the board or
> > visa versa and I see a propagation delay, so what am I missing?
> >
> > Joel
> >
> >
> > -----Original Message-----
> > From: SILR [mailto:silr@xxxxxxxxxxxx]
> > Sent: Thursday, March 13, 2008 6:27 PM
> > To: 'steve weir'; 'Joel Brown'
> > Cc: 'Istvan Novak'; si-list@xxxxxxxxxxxxx
> > Subject: RE: [SI-LIST] Re: Antwort: Re: Questions about interplane
> > capacitance
> >
> > Joel asked:
> > <<< ...why is charge propagation velocity not a factor when the PDN
> > is purely resistive? >>>
> >
> >
> > Well, here's a crazy way to think about this (which I'm sure not
> > everyone will agree)... I guess this would be like how Eric B. might
> > put it... "Be the Signal"
> >
> >
> > I'm the charge on some corner of a board...there's an IC in the
> > middle of the board...
> >
> > I have to get to that IC using this transmission line called the PDN.
> If
> > this Transmission Line had the classical Ls and Cs (and Rs) to
> > describe its characteristics, then that means I have to deal with
> > changing EM fields to get to that IC... but these time varying EM
> fields
> always cause some delay
> > in my charge getting to that IC in a timely manner...
> >
> > BUT!!! ...if this Transmission Line had nothing but Rs (no Ls and
> > Cs) to describe its characteristics then that means I don't have to
> > deal
> with
> time
> > varying EM fields any longer... I just have to deal with resistive
> losses
> > only but this only equates to a drop in Static Voltage Potential and
> > nothing more... (so keep the Z low!!!) And I can get there (to the
> > IC) in no time and the IC gets the charges that it needs and it
> > wouldn't even know anything is different...
> >
> > Again, this is a crazy way to look at this... but it works for me, for
> > now... until I get grilled by the senior members... :-)
> >
> > Silvester
> >
> > -----Original Message-----
> > From: si-list-bounce@xxxxxxxxxxxxx
> > [mailto:si-list-bounce@xxxxxxxxxxxxx] On Behalf Of steve weir
> > Sent: Thursday, March 13, 2008 5:57 PM
> > To: Joel Brown
> > Cc: 'Istvan Novak'; si-list@xxxxxxxxxxxxx
> > Subject: [SI-LIST] Re: Antwort: Re: Questions about interplane
> > capacitance
> >
> > Joel, it is transmission line theory. Think about an infinitely
> > long signal transmission line for a moment. At any instant a driver
> > sees a constant impedance across frequency. The voltage to current
> > relation is independent of prior history. What Istvan describes is
> > a very low impedance transmission structure for power.
> >
> > Sadly, a lot of IC vendors are still playing catch-up in terms of
> > power delivery. If they had their game together, they would be
> > telling
> you:
> > The actual voltage tolerances at the die, the current spectrum at
> > the die, and the parasitics of the die and package. From that you
> > could engineer your PDN. Instead often what we see are partial
> > recipes like
> you
> describe.
> > On a good day the recipes cost extra money. On a bad day, they
> > result in failures.
> >
> > One can build a resistive networks several ways. One is to add
> > discrete resistance by any number of methods, another is to use the
> > FDTIM method that Larry Smith has long championed. And even though
> > resistive networks have attractive qualities, reactive networks may
> > still be cheaper and equally effective. It all depends on the
> > circumstances. It is somewhat akin to surface finishes: there is
> > no ideal one. But there are several that when used properly work
> > very well. One just needs to respect the limitations of each method.
> >
> > Part of the problem figuring this stuff out is having sufficient
> > experience to judge trade-offs early in the design process. That's
> > just something that has to be learned. As more training materials
> > come out on power delivery, it will probably get easier. In the
> > shameless plug department, we ( Teraspeed ) do very nice jobs
> > optimizing power delivery systems for customers. If you've got a
> > design you want advice on we can get you squared-up pretty quickly.
> >
> > Best Regards,
> >
> >
> > Steve.
> > Joel Brown wrote:
> >
> >> Steve,
> >>
> >> So even though each cap has a relatively high ESR (1.6 Ohms) the
> >> PDN as a whole has a relatively low impedance which will result in
> >> low noise on the PDN. This goes against intuition and previous
> >> thinking that an IC needs a local bypass with low ESR and ESL to
> >> supply the needed charge during switching transients. I am starting
> >> to see that mathematically a resistive PDN lowers noise compared to
> >> one that is the inductive (you did a good job explaining that). The
> >> thing that I am having trouble grasping or
> >>
> > visualizing
> >
> >> is that why is charge propagation velocity not a factor when the
> >> PDN is purely resistive? Is the PDN model simply a resistor in
> >> series with the
> >>
> > load
> >
> >> and distance has no effect? Perhaps there is an analogy that would
> >> make
> >>
> > this
> >
> >> concept easier to understand? Also, when I see app notes from IC
> >> vendors that recommend using a 0.1uF and 1000pF cap on each supply
> >> pin and then instead I use distributed high ESR capacitors I feel
> >> like I am doing something quite different and contrary from the
> >> recommended and when I
> >>
> > query
> >
> >> the vendors on how they arrived at recommendations in the app note
> >> the answer I get is "we recommend that you do it exactly as shown
> >> in the app note, we know it works that way and if you don't follow
> >> it it may not
> >>
> > work".
> >
> >> Also I am wondering how all this relates to X2Y caps, I suppose
> >> they could be used with series resistors but that would somewhat
> >> defeat the purpose
> >>
> > by
> >
> >> adding inductance. Its not clear to me what approaches I should
> >> attempt on future designs.
> >>
> >> Joel
> >>
> >>
> >> -----Original Message-----
> >> From: si-list-bounce@xxxxxxxxxxxxx
> >> [mailto:si-list-bounce@xxxxxxxxxxxxx]
> >>
> > On
> >
> >> Behalf Of steve weir
> >> Sent: Wednesday, March 12, 2008 11:26 PM
> >> To: Doug Brooks
> >> Cc: Istvan Novak; si-list@xxxxxxxxxxxxx
> >> Subject: [SI-LIST] Re: Antwort: Re: Questions about interplane
> >> capacitance
> >>
> >> Doug, Istvan's representations are analytically exact. When the
> >> characteristic impedance of the transmission structure is high,
> >> and/or the rise times are slow then capacitors can be placed in
> >> close enough
> >>
> > proximity
> >
> >> that they load the transmission structure so as to make it appear a
> >> lower impedance with some little bumps. For example if one had a 10"
> >> x 10" 4
> >>
> > mil
> >
> >> er4.0 board =3D 22.5nF and loaded it with bypass every square inch of
> >> 150pH, then for slow enough signals, the distributed impedance
> >> would look like 80mOhms. If the network were constructed from 200
> >> capacitors, an ESR
> >>
> > value
> >
> >> of 1.6Ohms / cap would make that impedance uniform down to the RC
> >> knee of the parts. Assume that were matched by an AVP regulator of
> >> 80mOhms and
> >>
> > the
> >
> >> entire thing looks like 80mOhms from DC to over 1GHz. 80mOhms
> >> would
> >>
> > support
> >
> >> a 32 bit transition w/ about 5% droop. The impedance scales with
> >>
> > dielectric
> >
> >> height and the inverse square root of eR. Scale the dielectric
> >> down to 0.1mils and now 320 lines can switch simultaneously in one
> >> direction with
> >>
> > 5%
> >
> >> droop, and at arbitrary edge rates.
> >>
> >> Istvan has shown using analysis with the reverse pulse technique an
> >> inductive PDN shunt impedance acts like a noise high pass filter (
> >> See DC papers from at least as far back as DC East 2005 ). Put in
> >> a square wave noise pulse ( load current ) and the leading edge
> >> changes by Vdelta =3D -L*di/dt below the baseline. Allow the pulse
> >> to persist long enough and
> >>
> > the
> >
> >> system recovers back to the baseline which would be -I*Rpdn.
> >> Return the load current to zero, and now the energy stored in the
> >>
> > inductance
> >
> >> kicks back -L*di/dt. The p-p noise is then 2*Ldi/dt - (Imax-
> Imin)*Rpdn.
> >>
> > If
> >
> >> Rpdn is very small then it approximates 2*Ldi/dt.
> >> This behavior is apparent in the transient response plots of
> >> virtually any non-AVP VRM.
> >>
> >> Now, suppose that the VRM and PDN can be made to appear resistive
> >> right through Fknee. Then the response to a current pulse of I is
> >> simply Vdelta
> >>
> > =3D
> >
> >> -I*Rpdn. There is no component of di/dt, and so the total p-p
> >> noise is
> >>
> > just
> >
> >> (Imax - Imin)*Rpdn. AVP schemes position the DC operating point
> >> intentionally high so that at Imin they are at their margined high
> >> limits and at Imax they are at their low limits. This allows
> >> increasing Rpdn
> >>
> > while
> >
> >> still meeting the same current and voltage specifications.
> >>
> >> Best Regards,
> >>
> >>
> >> Steve.
> >>
> >>
> >> Doug Brooks wrote:
> >>
> >>
> >>> Istvan,
> >>>
> >>> With all due respect, I would modify your argument a little bit.
> >>> In very simplistic terms, suppose we need x amount of charge to
> >>> transition from a zero to a one in one ns. That amount of charge
> >>> (I
> >>> suggest) must be within
> >>> 6 inches of the need (what I think we are referring to as the
> >>> service radius). If not, it takes a little longer to reach the
> >>> logical
> one state.
> >>> I look at it, not from the standpoint of a dip in the rail, as
> >>> much as the ability to satisfy the rise time requirement (unless
> >>> you are referring to a dip in the rail that occurs during the rise
> >>> time
> >>> itself.) In the slightly longer term, the charge will replenish
> >>> fairly quickly, but not, perhaps fast enough to meet the rise time
> >>>
> > requirement.
> >
> >>> Doug Brooks
> >>>
> >>>
> >>>
> >>>
> >>>
> >>>
> >>>> Andreas,
> >>>>
> >>>> Yes and no. It is true that charge moves with finite speed, so
> >>>> for any given time duration the charge has to come from locations
> >>>> closer than the ratio of distance over speed. BUT the whole
> >>>> notion of service radius is based on the assumption that as you
> >>>> deplete the charge available in the immediate vicinity of the
> >>>> active device, you have to wait for replenishment, otherwise you
> >>>> get a big dip on the supply rail.
> >>>>
> >>>> Having a matched
> >>>> transmission medium to deliver power to the active device, the
> >>>> charge moves without interruption, and as you deplete the planes
> >>>> close to the device, it gets replenished on the fly from areas
> >>>> further away, so the service area concept is pretty much
> >>>> meaningless in this scenario. Current flows without interruption.
> >>>> The bucket brigade of infinitesimally small inductive and
> >>>> capacitive elements of the transmission line transmits the power
> continuously.
> >>>> If the load current changes, for any I(t) time function of load
> >>>> current, the transient noise at the load point will be I(t)*Zo,
> >>>> where we assume that Zo is the resistive and frequency
> >>>> independent characteristic impedance of the transmission medium.
> >>>> This is a very simplistic one-dimensional model, but it gives a
> >>>> good insight of why the service radius matters only on PDNs where
> >>>> the network is not matched.
> >>>>
> >>>> Regards,
> >>>>
> >>>> Istvan Novak
> >>>> SUN Microsystems
> >>>>
> >>>>
> >>>>
> >>>>
> >>>>
> >>>> Andreas.Lenkisch@xxxxxxxxxx wrote:
> >>>>
> >>>>
> >>>>
> >>>>> Istvan,
> >>>>> I'm wodering a little about your comments to the service radius.
> >>>>> Independant if the impedance is resistive, we have still a
> >>>>> propagation time which would limit the service radius from my
> >>>>>
> >>>>>
> >> understanding.
> >>
> >>
> >>>>> Do I'm wrong?
> >>>>>
> >>>>> regards
> >>>>> Andreas
> >>>>>
> >>>>>
> >>>>>
> >>>>> Istvan Novak <istvan.novak@xxxxxxxxxxx> Gesendet von:
> >>>>> si-list-bounce@xxxxxxxxxxxxx
> >>>>> 11.03.2008 13:14
> >>>>>
> >>>>> An
> >>>>> Joel Brown <joel@xxxxxxxxxx>
> >>>>> Kopie
> >>>>> si-list@xxxxxxxxxxxxx
> >>>>> Thema
> >>>>> [SI-LIST] Re: Questions about interplane capacitance
> >>>>>
> >>>>>
> >>>>>
> >>>>>
> >>>>>
> >>>>>
> >>>>> Joel,
> >>>>>
> >>>>> Just one quick comments to the good summary from Steve:
> >>>>>
> >>>>> While considering planes and bypass capacitors in terms of
> >>>>> effective capacitances and inductances is a valid approach, we
> >>>>> need to keep in mind that focusing on the capacitive or
> >>>>> inductive nature of parts without looking at the wider picture
> >>>>> misses a very important and useful class of solutions, namely
> >>>>> that of matched transmission lines. As it was pointed out
> >>>>> earlier several times on the SI list, the best
> >>>>> (self) impedance for a power distribution network is a resistive
> >>>>> one, neither capacitive, nor inductive.
> >>>>> We can get resistive impedance from a matched transmission line,
> >>>>> regardless of its capacitance and inductance, and in such cases
> >>>>> the notion of 'service area' of parts become meaningless: you
> >>>>> can put bypass components further away from the active devices
> >>>>> without sacrificing performance.
> >>>>>
> >>>>> Regards,
> >>>>>
> >>>>> Istvan Novak
> >>>>> SUN Microsystems
> >>>>>
> >>>>> Joel Brown wrote:
> >>>>>
> >>>>>
> >>>>>
> >>>>>
> >>>>>> Interplane capacitance is frequently cited as the only
> >>>>>> effective bypass capacitance on a PCB at frequencies above 200 MHz=
.
> >>>>>> I am currently working on a design which brings up some
> >>>>>> questions
> >>>>>>
> >>>>>>
> >>>>>>
> >>>>>>
> >>>>> regarding
> >>>>>
> >>>>>
> >>>>>
> >>>>>
> >>>>>> interplane capacitance.
> >>>>>>
> >>>>>> 1. Power planes normally carry "standard" voltage rails that
> >>>>>> are used throughout a board such as +5V and +3.3V.
> >>>>>> High speed ICs usually have core voltages that are local to the
> >>>>>> IC and
> >>>>>>
> >>>>>>
> >>>>>>
> >>>>>>
> >>>>> are
> >>>>>
> >>>>>
> >>>>>
> >>>>>
> >>>>>> provided by a local regulator which converts the standard rail
> >>>>>> to the
> >>>>>>
> >>>>>>
> >>>>>>
> >>>>>>
> >>>>> core
> >>>>>
> >>>>>
> >>>>>
> >>>>>
> >>>>>> voltage (example 3.3 to 1.8V).
> >>>>>> The local core voltage is distributed on a plane area that is
> >>>>>> local to
> >>>>>>
> >>>>>>
> >>>>>>
> >>>>>>
> >>>>> the
> >>>>>
> >>>>>
> >>>>>
> >>>>>
> >>>>>> IC and therefore is small in area (0.25 sq in or less) which
> >>>>>> results in
> >>>>>>
> >>>>>>
> >>>>>>
> >>>>>>
> >>>>> a
> >>>>>
> >>>>>
> >>>>>
> >>>>>
> >>>>>> very small amount of interplane capacitance.
> >>>>>> Is this very small amount of capicitance effective for
> >>>>>> bypassing the IC?
> >>>>>>
> >>>>>>
> >>>>>>
> >>>>>>
> >>>>> I
> >>>>>
> >>>>>
> >>>>>
> >>>>>
> >>>>>> am sure it depends somewhat on the current waveform being drawn
> >>>>>> by the
> >>>>>>
> >>>>>>
> >>>>>>
> >>>>>>
> >>>>> IC
> >>>>>
> >>>>>
> >>>>>
> >>>>>
> >>>>>> but this can only be estimated because semiconductor
> >>>>>> manufacturers do
> >>>>>>
> >>>>>>
> >>>>>>
> >>>>>>
> >>>>> not
> >>>>>
> >>>>>
> >>>>>
> >>>>>
> >>>>>> provide current consumption profile as a function of frequency.
> >>>>>> To make matters worse, some ICs have several different VCC pins
> >>>>>> which the manufacturer recommends connecting to separate
> >>>>>> networks of bypass caps
> >>>>>>
> >>>>>>
> >>>>>>
> >>>>>>
> >>>>> and
> >>>>>
> >>>>>
> >>>>>
> >>>>>
> >>>>>> ferrite beads. This cuts the power distributuion up even more
> >>>>>> resulting
> >>>>>>
> >>>>>>
> >>>>>>
> >>>>>>
> >>>>> in
> >>>>>
> >>>>>
> >>>>>
> >>>>>
> >>>>>> less (practically zero) interplane capacitance. It is somewhat
> >>>>>> ironic
> >>>>>>
> >>>>>>
> >>>>>>
> >>>>>>
> >>>>> that
> >>>>>
> >>>>>
> >>>>>
> >>>>>
> >>>>>> the the voltages such as +5V and +3.3V which are required at
> >>>>>> points
> >>>>>>
> >>>>>>
> >>>>>>
> >>>>>>
> >>>>> across
> >>>>>
> >>>>>
> >>>>>
> >>>>>
> >>>>>> the whole board and therefore have the most interplane
> >>>>>> capacitance are
> >>>>>>
> >>>>>>
> >>>>>>
> >>>>>>
> >>>>> also
> >>>>>
> >>>>>
> >>>>>
> >>>>>
> >>>>>> the voltages which have least requirement for interplane
> >>>>>> capacitance
> >>>>>>
> >>>>>>
> >>>>>>
> >>>>>>
> >>>>> because
> >>>>>
> >>>>>
> >>>>>
> >>>>>
> >>>>>> they do not directly supply high speed rails.
> >>>>>>
> >>>>>> 2. There has been a lot of emphasis on reducing the mounted
> >>>>>> inductance
> >>>>>>
> >>>>>>
> >>>>>>
> >>>>>>
> >>>>> of
> >>>>>
> >>>>>
> >>>>>
> >>>>>
> >>>>>> bypass capacitors. Even with this reduced inductance they are
> >>>>>> still only effective up to several hundereds of MHz at which
> >>>>>> point the interplane capacitance becomes the only bypass
> >>>>>> capacitance mechanism. However there
> >>>>>>
> >>>>>>
> >>>>>>
> >>>>>>
> >>>>> is
> >>>>>
> >>>>>
> >>>>>
> >>>>>
> >>>>>> inductance between the connection of the IC to the planes. This
> >>>>>>
> >>>>>>
> >>>>>>
> >>>>>>
> >>>>> inductance
> >>>>>
> >>>>>
> >>>>>
> >>>>>
> >>>>>> consists of vias and package inductance. I did look for some
> >>>>>> numbers for package inductance and did not find much, it seems
> >>>>>> to be a closely held secret. Also it is unknown how much bypass
> >>>>>> capacitnace is internal to
> >>>>>>
> >>>>>>
> >>>>>>
> >>>>>>
> >>>>> the IC
> >>>>>
> >>>>>
> >>>>>
> >>>>>
> >>>>>> package. Just for example if we assume 250pH for the vias and
> >>>>>> 500 pH for
> >>>>>>
> >>>>>>
> >>>>>>
> >>>>>>
> >>>>> the
> >>>>>
> >>>>>
> >>>>>
> >>>>>
> >>>>>> package, then the impedance at 500 MHz would be 2.36 Ohms. This
> >>>>>> seems
> >>>>>>
> >>>>>>
> >>>>>>
> >>>>>>
> >>>>> rather
> >>>>>
> >>>>>
> >>>>>
> >>>>>
> >>>>>> high for the interplane capacitance to be of much benefit.
> >>>>>>
> >>>>>> In summary how much interplane capacitance is needed to be
> >>>>>> beneficial,
> >>>>>>
> >>>>>>
> >>>>>>
> >>>>>>
> >>>>> and
> >>>>>
> >>>>>
> >>>>>
> >>>>>
> >>>>>> why is it beneficial given the inductance in the vias and package?
> >>>>>>
> >>>>>> Thanks - Joel
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