FreeLists / si-list / [SI-LIST] Buried capacitance and vias

["Shawn Arnold" <shawn@xxxxxxxxxxxxxxxxxxxxxxxx>]

Hi All,
 
There are a number of buried capacitance material solutions out there
for us to chose from and in most applications we try to place these
cores at the outside edges of the PCB to minimize via inductance. The
issue I'm having is that the PCB I'm working on is very component dense,
back-to-back BGAs both sides and we need to blind via from the outer
layers, thru atleast one GND plane for routing. The PCB will require 6
internal signal layers and 4 differing power planes. Due to the
component density, we'd like to remove as many bypass caps as possible.
The PCB is 9"x3" and has a DDR2 controlled impedance memory bus which
cannot be exclusively routed microstrip.
 
How much benefit of the buried capacitance, thus removal of BP caps,
will be lost in each instance?
 
Option 1- Place two PWR/GND cores (4 layers total) on each outside edge
of the PCB then blind via to the 6th layer deep from each surface on an
18 layer, .093 thick PCB. The big downside is that the planes on the
"opposite" side of the stack need to power devices on both sides of the
PCB, long small vias (I cannot increase the PWR via diameter).
 
Option 2- Place the 4 PWR planes and their corresponding GNDs in the
center of a 20 layer, .093 thick, heavier copper PCB to equalize the via
inductances and give priority to the blind trace vias on outer routing
layers.
 
Option 3- Place four PWR/GND cores (8 layers total), one for each
voltage, on the outer edges of the PCB and force all of the signal
routing to the middle of a 26 layer .155 thick PCB.
 
Option 4- Your ideas... 
 
Regards,
Shawn
 
 

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