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[SI-LIST] FW: Re: Ground bounce (was VOH datasheet question)
- From: "Howard Johnson" <howie03@xxxxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Tue, 14 Mar 2006 22:27:10 -0800
Dear Edi et. al.,
I'm not sure what situation you have in mind, but I should
point that increased capacitive loading can indeed cause
additional ground bounce under some rather special
circumstances. You may wish to argue that these
circumstances do not apply to your situation, but,
nevertheless, here is my thinking.
First, I suppose the capacitive load is connected very close
to the driver, within a small fraction of one risetime.
Next, imagine there are NO OTHER LOADS.
Under this situation the output current is ZERO and there is
no appreciable "ground bounce".
Now make the capacitor larger (non-zero). Output current
happens, and so does "ground bounce".
What could be simpler? Increasing the capacitive load from
zero to a finite value causes more ground bounce. The
difference here between your analysis and mine is that I
started from "nothing". You seem to have started with a big
value of C and then postulated making it even bigger.
For a driver with nominal output impedance RS consider the
range of small capacitances with values C such that the
time-contant product C*RS is LESS than the natural
open-circuit response time of the driver. In this range
(again assuming a closely-connected capacitor), increasing
the capacitance increases the dI/dt. Beyond that range
(larger C) the dI/dt saturates at a maximum value (i.e., the
driver has time to work up to full output strength before
the capacitor begins to charge).
Example: For a driver with RS=25 ohms and an open-circuit
(unloaded) switching time of 500 ps, any closely-connected
capacitor less than 20 pF falls into the "small capacitor"
category. Changing from 10 pF to 20 pF loading I would
expect to see some increase in the dI/dt leaving the
package.
I will certainly agree that if the capacitor is located
rather far from the driver (more than 1/2 a risetime), then
its effect does not affect events during the first rising
edge. With some chips, you can't even get out of the package
within half a risetime, so for those types of devices
capacitive loading would likely not exacerbate ground
bounce.
Your thoughts?
Best regards,
Dr. Howard Johnson, Signal Consulting Inc.,
tel +1 509-997-0505, howie03@xxxxxxxxxx
http:\\sigcon.com -- High-Speed Digital Design seminars,
publications and films
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Muranyi,
Arpad
Sent: Tuesday, March 14, 2006 7:20 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Ground bounce (was VOH datasheet
question)
Edi,
Not necessarily. Consider this situation:
The capacitor acts as an AC short. This means that
as a (fast) buffer switches, it will initially have=20
to drive a full short circuit current. Contrast=20
that with a resistive load, where the output voltage
will always follow a divider ratio as determined
by the buffer and the load resistor. In this case
the current will never reach the levels that you
would see with a capacitive load.
Arpad Muranyi
Intel Corporation
------------------------------------------------------
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx] =
On Behalf Of Edi Fraiman
Sent: Tuesday, March 14, 2006 3:43 AM
To: hmurray@xxxxxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Ground bounce (was VOH datasheet
question)
Hi,
I concur with you.
Increased capacitive load reduce the slew rate on the driver
outputs.
The slower the output slew rate, the lower the ground bounce
will be.
Edi
=3D20
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]
> On Behalf Of Hal Murray
> Sent: Tuesday, March 14, 2006 12:26 PM
> To: si-list@xxxxxxxxxxxxx
> Cc: hmurray@xxxxxxxxxxxxxxx
> Subject: [SI-LIST] Ground bounce (was VOH datasheet
question)
>=3D20
>=3D20
> > You could clarify this issue from Dr. Johnson article
named "Big
> > Buffer" (http://www.sigcon.com/Pubs/news/8_07.htm).
>=3D20
> As usual, his stuff is very good reading.
>=3D20
> This paragraph caught my attention.
>=3D20
> > The main factors that affect SSO noise are (1) the
aggregate amount
of
> > current switched by your IC, (2) the rise time of that
current, and
> > (3) the number and quality of the power and ground
connections
> > provided in the IC package. Most relevant to this
discussion is the
> > total amount of current--more capacitive loading
enlarges that
> > current, increasing the amplitude of SSO noise.
>=3D20
> Why does more capacitive loading make SSO worse?
>=3D20
> The previous discussion showed that you can compute the
output
resistance
> of
> the driver from the short circuit current. That doesn't
depend upon
the
> capacitive loading.
>=3D20
> I think that capacitive loading will make the duration of
the output
> current
> pulse longer. It will slow down the rise time of the
signal, but
that's
> the
> voltage rise time. The current rise time is what causes
ground bounce
and
> that won't change if you add more load capacitance.
>=3D20
> What am I missing?
>=3D20
> Is the turn-on time for a driver slow rather than
instantaneous?
"Slow"
> meaning roughly the same as the (normal) rise time so the
normal
> capacitance
> gets charged while the driver is turning on and the driver
never
delivers
> the
> full short circuit current?
>=3D20
>=3D20
>=3D20
> --
> The suespammers.org mail server is located in California.
So are all
my
> other mailboxes. Please do not send unsolicited bulk
e-mail or
> unsolicited
> commercial e-mail to my suespammers.org address or any of
my other
> addresses.
> These are my opinions, not necessarily my employer's. I
hate spam.
>=3D20
>=3D20
>=3D20
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Other related posts:[SI-LIST] FW: Re: Ground bounce (was VOH datasheet question)
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