FreeLists / si-list / [SI-LIST] Re: Ground bounce (was VOH datasheet question)

[Scott McMorrow <scott@xxxxxxxxxxxxx>]

Just to throw a bit of a wrench into this.  If the load capacitance is 
placed more than one half the output rise time away from the driver, 
there is zero impact on SSO on the Initial Switching Transient.  (i.e. - 
the driver has no information which lets it know that a load capacitance 
exists, until the load reflects the traveling wave.)  It is only after 
the load is reflected back to the driver that it "sees" the 
capacitance.  Since capacitance starts out looking like a low impedance 
discontinuity, this appears to the driver as a dynamic change in the 
load impedance, which it compensates for by driving a secondary current 
transient, and subsequently an additional SSO transient, which occurs at 
a different point in time.  This so-called "reflected" SSO transient, 
can be timed to cause upset of DQS strobes, due to DQ switching in 
modern source synchronous busses, and is load and interconnect length 
dependent.
In most "interesting" busses, loads are always greater than 1/2 rise 
time away from the driver.  In these cases, load capacitance looks like 
a dynamic impedance discontinuity at the end of the line, and has no 
effect on the rise/fall time of the initial driver switching transient.  
It is only on subsequent switching events, where load capacitance makes 
it's impact known.  This impact depends upon the timing of the reflected 
capacitive discontinuity.  In the frequency domain, this looks like a 
quarter wave resonance point.  There are certain points in the frequency 
spectrum where this reflected capacitance can either cause constructive 
or destructive reinforcement of the bit pattern being transmitted.  
These cause severe ringing and overshoot, or severe attenuation of the 
pulses.  If the pattern is right, and the timing is right, you can most 
certainly cause a significant increase in SSO, resonances and even 
oscillations.


regards,

Scott

Scott McMorrow
Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882
(401) 284-1827 Business
(401) 284-1840 Fax

http://www.teraspeed.com

Teraspeed® is the registered service mark of
Teraspeed Consulting Group LLC



Bill Wurst wrote:
> Edi,
>
> This is a common misconception.  If you perform a cursory analysis, you 
> will find that loading an output with more capacitance, while it 
> increases the transition time (decreases the slew rate), does not change 
> the amplitude of the rail bounce but it does have the undesirable effect 
> of extending its duration.
>
>      -Bill
>
>
>        /************************************
>       /         billw@xxxxxxxxxxx         /
>      /                                   /
>     / Advanced Electronic Concepts, LLC /
>    /           www.aec-lab.com         /
>    ************************************
>
> Edi Fraiman wrote:
>   
>> Hi,
>>
>> I concur with you.
>> Increased capacitive load reduce the slew rate on the driver outputs.
>> The slower the output slew rate, the lower the ground bounce will be.
>>
>> Edi
>> =20
>>
>>
>>
>>     
>>> -----Original Message-----
>>> From: si-list-bounce@xxxxxxxxxxxxx
>>>       
>> [mailto:si-list-bounce@xxxxxxxxxxxxx]
>>
>>     
>>> On Behalf Of Hal Murray
>>> Sent: Tuesday, March 14, 2006 12:26 PM
>>> To: si-list@xxxxxxxxxxxxx
>>> Cc: hmurray@xxxxxxxxxxxxxxx
>>> Subject: [SI-LIST] Ground bounce (was VOH datasheet question)
>>> =20
>>> =20
>>>
>>>       
>>>> You could clarify this issue from Dr. Johnson article named "Big
>>>> Buffer" (http://www.sigcon.com/Pubs/news/8_07.htm).
>>>>         
>>> =20
>>> As usual, his stuff is very good reading.
>>> =20
>>> This paragraph caught my attention.
>>> =20
>>>
>>>       
>>>> The main factors that affect SSO noise are (1) the aggregate amount
>>>>         
>> of
>>
>>     
>>>> current switched by your IC, (2) the rise time of that current, and
>>>> (3) the number and quality of the power and ground connections
>>>> provided in the IC package. Most relevant to this discussion is the
>>>> total amount of current--more capacitive loading enlarges that
>>>> current, increasing the amplitude of SSO noise.
>>>>         
>>> =20
>>> Why does more capacitive loading make SSO worse?
>>> =20
>>> The previous discussion showed that you can compute the output
>>>       
>> resistance
>>
>>     
>>> of
>>> the driver from the short circuit current.  That doesn't depend upon
>>>       
>> the
>>
>>     
>>> capacitive loading.
>>> =20
>>> I think that capacitive loading will make the duration of the output
>>> current
>>> pulse longer.  It will slow down the rise time of the signal, but
>>>       
>> that's
>>
>>     
>>> the
>>> voltage rise time.  The current rise time is what causes ground bounce
>>>       
>> and
>>
>>     
>>> that won't change if you add more load capacitance.
>>> =20
>>> What am I missing?
>>> =20
>>> Is the turn-on time for a driver slow rather than instantaneous?
>>>       
>> "Slow"
>>
>>     
>>> meaning roughly the same as the (normal) rise time so the normal
>>> capacitance
>>> gets charged while the driver is turning on and the driver never
>>>       
>> delivers
>>
>>     
>>> the
>>> full short circuit current?
>>> =20
>>> =20
>>> =20
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