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[SI-LIST] Re: Effects of overshoot/undershoot on long-term reliability

  • From: "Mikhail Matusov" <matusov@xxxxxxxxxxxx>
  • To: <si-list@xxxxxxxxxxxxx>
  • Date: Thu, 9 Mar 2006 11:00:01 -0500
Jai,

Yes, I thought of this too. The chip doesn't have any drive
strength/impedance control. With regards to lowering the voltage, I don't
have much room for additional regulation and 10% is not likely to fix the
problem anyway... I think we are going to buy the bullet and redesign the
board to include the resistors.

Thanks,
=======================
Mikhail Matusov
Hardware Design Engineer
Square Peg Communications
Tel.: +1 (613) 271-0044 ext.231
Fax: +1 (613) 271-3007
http://www.squarepeg.ca



----- Original Message ----- 
From: "Jai Shanker" <jswarrier@xxxxxxxxx>
To: <matusov@xxxxxxxxxxxx>; <si-list@xxxxxxxxxxxxx>
Sent: Thursday, March 09, 2006 5:59 AM
Subject: Re: [SI-LIST] Re: Effects of overshoot/undershoot on long-term
reliability


> Hi,
>
> You may have already tried this:
>
> 1. Is it possible to vary the driver impedance in the
> DRAM ( OCD / other driver impedance control in EMRS
> reg) then set it to weak/ low.
>
> 2. Is it possible to operate the DRAM at its lowest
> allowable Vdd (3.3V - 10%) that may get you some
> margin in the overshoots?
>
> regards,
> Jai
>


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