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Thread Index for si-list, 03-2005

[si-list] || [03-2005 Date Index] [03-2005 Thread Index]

  1. [SI-LIST] A question on DDR Clock, MJA
  2. [SI-LIST] IBIS Model, Thiago Wellington Joazeiro Almeida
  3. [SI-LIST] IBIS model request for SDRam, Grasso, Charles
  4. [SI-LIST] Re: IBIS model request for SDRam, Muranyi, Arpad
  5. [SI-LIST] What is probability distribution for logic switching, Kai Keskinen
  6. [SI-LIST] Re: IBIS and SI talks at Mentor' User2User Conference, Pillie, Max
  7. [SI-LIST] best tool for emc, sub mani
  8. [SI-LIST] A question about IBIS usage method, Heinrich.Smith
  9. [SI-LIST] Re: A question about IBIS usage method, Muranyi, Arpad
  10. [SI-LIST] Re: creating an IBIS model..., zhangfeng
  11. [SI-LIST] Re: A IBIS question about usage method, Heinrich.Smith
  12. [SI-LIST] Re: What is probability distribution for logic switching, Peterson, James F (FL51)
  13. [SI-LIST] about pspice, praveen_vrec_123
  14. [SI-LIST] Re: Is it ok to route the hi speed connector trace in low speed connector area, Grasso, Charles
  15. [SI-LIST] Long T reflection problems, Stein, James F (UK)
  16. [SI-LIST] Re: Long T reflection problems, kfrobinson
  17. [SI-LIST] Re: best tool for emc, Peter Fekete
  18. [SI-LIST] Paper on BGA crosstalk and power system, Mark Alexander
  19. [SI-LIST] Re: Electrically conductive Epoxy, dgun
  20. [SI-LIST] Sitching via, stitching cap usage for PCI Express, Heinrich.Smith
  21. [SI-LIST] Double Rising Waveform and Falling Waveform in one IBIS model, Heinrich.Smith
  22. [SI-LIST] Re: Paper on BGA crosstalk and power system, Wei Zhou
  23. [SI-LIST] European IBIS Summit @ DATe 2005 - Final Call for Participation + Preliminary Agenda, Ralf Bruening
  24. [SI-LIST] New Optimal Corp. Technical Paper Available, Optimal Corporation
  25. [SI-LIST] Re: Double Rising Waveform and Falling Waveform in one IBIS model, Beal, Weston
  26. [SI-LIST] to-can hfss, Kamran Azizi
  27. [SI-LIST] Re: Long T reflection problems....test post, please ignore, Mike Greim
  28. [SI-LIST] Re: dielectric material-Isola IS620, Hargin, Bill
  29. [SI-LIST] Re: dieclectric material-Isola IS620, Lee Ritchey
  30. [SI-LIST] Why not Cytop as dielectric?, Peter Salmon
  31. [SI-LIST] EISA EDGE CONNECTOR, mahesh.linge
  32. [SI-LIST] AW: dieclectric material-Isola IS620, Sol Tatlow
  33. [SI-LIST] how to measure the propagation delay of rlc circuit using pspice, praveen_vrec_123
  34. [SI-LIST] FW: Re: Paper on BGA crosstalk and power system (Altera Responds), Tegan Campbell
  35. [SI-LIST] Re: FW: Re: Paper on BGA crosstalk and power system (Altera Responds), steve weir
  36. [SI-LIST] SI-related jobs at Sigrity, Teo Yatman
  37. [SI-LIST] PCI Express Applications Engineer at Altera, George Carlson
  38. [SI-LIST] Staff Signal Integrity Engineer Position Open in Harrisburg PA, Bergey, Dana
  39. [SI-LIST] Package parasitic in Pb free component ??, sivagurunathan
  40. [SI-LIST] Re: FW: Re: Paper on BGA crosstalk and power system, Tegan Campbell
  41. [SI-LIST] package SSN model accuracy requirements, Heyfitch
  42. [SI-LIST] March-2005 IEEE-EMCS Santa Clara Valley chapter meeting (3-8-2005), Ahmad Fallah
  43. [SI-LIST] Distributed RLC from S-parameter data, Yaron Kretchmer
  44. [SI-LIST] unsubscribe, Balakrishnan K
  45. [SI-LIST] Layout Considerations!!!, Paul Gingras
  46. [SI-LIST] Re: Layout Considerations!!!, Mike Greim
  47. [SI-LIST] cancel me from emaile, wisal ahmed
  48. [SI-LIST] cancel me from email, wisal ahmed
  49. [SI-LIST] Re: package SSN model accuracy requirements, Chris Cheng
  50. [SI-LIST] Help needed for Pspice sim, naren singh
  51. [SI-LIST] Signal Integrity tool evaluation, Pankaj Kakkar
  52. [SI-LIST] don't read the instructions: quick cable quality test, Doug Smith
  53. [SI-LIST] max operating frequency of pspice?, praveen_vrec_123
  54. [SI-LIST] Re: max operating frequency of pspice?, Beal, Weston
  55. [SI-LIST] Device Characterization Openings at Altera Corp., San Wong
  56. [SI-LIST] FastCap - How to use it?, Fatima Bocoum
  57. [SI-LIST] DDR SDRAM / Xilinx warning, Peterson, James F (FL51)
  58. [SI-LIST] Re: DDR SDRAM / Xilinx warning, Peterson, James F (FL51)
  59. [SI-LIST] RMCEMC Presentation downloads, Charles Grasso
  60. [SI-LIST] Interview questions, reggie king
  61. [SI-LIST] Re: Splitting this power plane - And GND planes count, Sol Tatlow
  62. [SI-LIST] Hi guys, well I'm studying SI I'm a newbie but I have a question..., Néstor Hernández Cruz
  63. [SI-LIST] something about the connection of shunt match resistors, ZHAO DAVE
  64. [SI-LIST] Re: RMCEMC Presentation downloads, Grasso, Charles
  65. [SI-LIST] Prepare for your NARTE EMC Certification, Grasso, Charles
  66. [SI-LIST] stripline with split-plane, Zhangkun
  67. [SI-LIST] reference plane of W element, zam jawa
  68. [SI-LIST] question about the shunt match resistors with stub, ZHAO DAVE
  69. [SI-LIST] Derivation of CFL limit for FDTD, Yaron Kretchmer
  70. [SI-LIST] New SI appnotes, Dima Smolyansky
  71. [SI-LIST] original circuit data (was: package SSN model accuracy requirements), Dimiter Popoff
  72. [SI-LIST] Re: reference plane of W element, Robert Washburn
  73. [SI-LIST] IBIS 4.1 Golden Syntax parser available for download!, Mirmak, Michael
  74. [SI-LIST] Re: package SSN model accuracy requirements, now Behavioral Modeling, Donald Telian
  75. [SI-LIST] Re: package SSN model accuracy requirements, now Behavioral Modeling, steve weir
  76. [SI-LIST] Proximity and gound plane return model, Mark Burford
  77. [SI-LIST] SSTL/HSTL classes, shekhar sharma
  78. [SI-LIST] Re: Transmission line impedance is related to signal switching frequency ?, Doug Hopperstad
  79. [SI-LIST] Ansoft Models, Euan Mowat
  80. [SI-LIST] HSPICE S-paramter questions, Ed Sayre III
  81. [SI-LIST] Re: HSPICE S-paramter questions, Craig Clewell
  82. [SI-LIST] -+48V power plane, ma mu
  83. [SI-LIST] Re: -+48V power plane, Lee Ritchey
  84. [SI-LIST] ICM Parser Version 1.1 Available!, Mirmak, Michael
  85. [SI-LIST] High voltage (3kV) precautions, nagaraj
  86. [SI-LIST] FastCap and magnetic field, Fatima Bocoum
  87. [SI-LIST] SI Problem !!!, Naren
  88. [SI-LIST] 2.24 Gb/s over standard 2mm HM connectors?, Mikhail Matusov
  89. [SI-LIST] Re: 2.24 Gb/s over standard 2mm HM connectors?, Bob Sullivan
  90. [SI-LIST] Microstrip line loss on Rogers 4350, Ming Tsai
  91. [SI-LIST] question about the bypass cap, david
  92. [SI-LIST] Re: package SSN model accuracy requirements, now B ehavioral Modeling, Chris Cheng
  93. [SI-LIST] 回复:question about the bypass cap, zhangkun 29902
  94. [SI-LIST] Re: now Behavioral Modeling, Pratt, Gary
  95. [SI-LIST] IBIS model package parasitics, Mark . Webber
  96. [SI-LIST] Re: Microstrip line loss on Rogers 4350, Loyer, Jeff
  97. [SI-LIST] Google Scholar search engine, Jim Antonellis
  98. [SI-LIST] Minimum eye opening of 8b10b encoded signals, Michael.Kurten
  99. [SI-LIST] Bus Transceivers & Termination Resistors, Chinmoy Raj H
  100. [SI-LIST] DDR2 Clock question, Bill Wurst
  101. [SI-LIST] Re: DDR2 Clock question, Hassan O. Ali
  102. [SI-LIST] Re: Minimum eye opening of 8b10b encoded signals, Chris Cheng
  103. [SI-LIST] LVDS differential crosstalk question, ma mu
  104. [SI-LIST] Re: LVDS differential crosstalk question, Hargin, Bill
  105. [SI-LIST] Transmission Line, pomgud
  106. [SI-LIST] HSTL Logic, pomgud
  107. [SI-LIST] Decoupling analysis tools?, Fasig, Jonathan L.
  108. [SI-LIST] Re: Macromodeling, Muranyi, Arpad
  109. [SI-LIST] [Expert system], yous
  110. [SI-LIST] DDR Termination, Santangelo, Steven
  111. [SI-LIST] Re: DDR Termination, steve weir
  112. [SI-LIST] Questions about impurity in dielectric material., Peng Ye
  113. [SI-LIST] Loss Tangent question, Doug Brooks
  114. [SI-LIST] Re: Loss Tangent question, Peter Fekete
  115. [SI-LIST] RapidIO timing, Peterson, James F (FL51)
  116. [SI-LIST] two new signal integrity pdf articles for download, Eric Bogatin
  117. [SI-LIST] Help on signal integrity, manish khemani
  118. [SI-LIST] jitter measurement, noam shamir
  119. [SI-LIST] Re: Help on signal integrity, prashant jaiswar
  120. [SI-LIST] DDR-II, Prakash N
  121. [SI-LIST] HSPICE S-element with a large number of ports, Hassan O. Ali
  122. [SI-LIST] mixed mode differential s-parameter processing and display software, Scott McMorrow
  123. [SI-LIST] Re: [Expert system], zhangkun 29902
  124. [SI-LIST] Re: DDR-II, Prakash N
  125. [SI-LIST] Re: 2 layer stack up with flooded ground and power, Ingo Kupper
  126. [SI-LIST] Re: 2 layer stack up with flooded ground and power, steve weir
  127. [SI-LIST] Re: HSPICE S-element with a large number of ports, Hassan O. Ali
  128. [SI-LIST] SPI 2005 - Call for Participation, Andre Grabinski
  129. [SI-LIST] ddr2, Prakash N
  130. [SI-LIST] output signal degradation of cmos inverter driving a RC line, praveen_vrec_123



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