FreeLists / si-list / [SI-LIST] Package parasitic in Pb free component ??

["sivagurunathan" <gsivaguru@xxxxxxxxxxx>]

Hi All,

Is there any exact impact on Package parasitic when you choose lead 
Free (Pb free) component?
If first level interconnect ( at die bump) is Pb free then we can 
expect certain amount of Parasitic change so that the IBIS model 
that we need to use for that component also should be different.( at 
least package parasitic).
And for Second level interconnects ( from component to PCB) also 
there is no exact RLC change info from component vendors?
Do we really need to look in to that?
Please suggest me the suitable.

Thanks in advance.
Regards,
Siva




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