FreeLists / si-list / [SI-LIST] Re: FW: Re: Paper on BGA crosstalk and power system (Altera Responds)

[steve weir <weirsi@xxxxxxxxxx>]

Tegan, Don,

As I said there is no free lunch.  How much good tying off I/Os provides 
depends on how the build-up and routing was done in the BGA.  I/Os have a 
long way to go to get back to the die.

If you use a sparse return chevron, then you can get clobbered by cross 
talk just in the Z axis, and burning up I/Os, changing I/O assignments, 
and/or working the coding are all option for dealing with the issue.  For 
example, if you are just running a single big synchronous bus in one 
direction, this kind of cross talk would impair the timing budget, but 
would be likely settle out cycle by cycle so would probably not cause 
signaling failures.  To handle both directions ( DDR ), and / or multiple 
busses careful I/O placement can do a lot to make even a low-cost wire bond 
package work in an application where careless  I/O placement would make a 
disaster.

The FPGA mfg's as makers of these do-all widgets get stuck determining 
which trade-offs to take.   Global comparisons are complicated by 
differences in pin and pin configuration options for each vendor's line.  I 
will be surprised if there is a reasonable application that cannot be made 
to work reliably with either mfg's parts.  But there is definitely user 
effort required to apply the components properly, and within their 
capabilities.   And naturally, the closer a user takes a part to its 
limits, the more careful and thorough the user engineering needs to be.

The right way to proceed is to simulate the I/O portion of the application 
with each candidate.  This will tell you how much margin you have, or 
don't, for the way you intend to use the part before accounting for the PDN 
issues.   Life then gets a little bit trickier.  In the best case you would 
create an evaluation vehicle consistent with your mfg. process.  If not, 
use one of the vendors' test boards, and extrapolate.


Steve.


At 10:10 AM 3/4/2005 -0700, Tegan Campbell wrote:
>Originally sent to Don, he suggested this might be interesting to everyone.
>
>Tegan
>
>
>Don,
>I am no expert on in-package crosstalk, but the biggest contributing factor
>to inductive crosstalk is how far away from a reference pin you are(if I
>remember my physics).  So, it seems that if you tie an I/O to a reference
>near pins that are actively sourcing/sinking current, wouldn't that reduce
>the loop area AND the shared currents through dedicated ground pins?  If I'm
>thinking about this correctly, what your team did is akin to what the Xilinx
>package designers force on you: a lot of pwr/gnd pins spread out around the
>package to reduce ball/ball crosstalk.
>Personally, I look at the results and say to myself "Hmm, I'd rather have a
>few more signal pins and more crosstalk."
>Anyway, that's how I view it.  We've done the same thing before in large
>FPGA designs before we even looked at signals.
>Just my $.02.
>Tegan
>
>-----Original Message-----
>From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
>Behalf Of Don Nelson
>Sent: Friday, March 04, 2005 8:51 AM
>To: SI List
>Subject: [SI-LIST] Re: Paper on BGA crosstalk and power system (Altera
>Responds)
>
>Thank you for your reply, Steve.
>One of the reasons that this debate between Xilinx and Altera is
>relevant to me is that our team is currently deciding between the
>Virtex-4 and the Stratix II for our next product.  Another group at my
>company used the Stratix I series and experienced excessive--and
>crippling, in their application--SSO noise.  They were able to improve
>matters *tremendously* by taking several unused outputs and internally
>driving them high or low, then tying them to the board ground or
>respective power plane.
>
>I have been trying to figure out how (if at all) this fits in with the
>measurements made by Howard Johnson and Mark Alexander.  It seems to me
>that if tying the stuck-high/low outputs to power/ground made a
>measurable difference in SSN, the power/ground bounce they were
>observing must have been due to PDN impedance in the die, rather than
>inductive crosstalk, since these newly purposed i/o would not attach to
>the package power and ground planes.  Their efforts may have reduced
>the impedance of the PDN, but would not have a significant effect on
>the inductive coupling between the signal I/Os in the package as
>demonstrated by Howard and Mark.  Indeed, I doubt that sticking a
>driven-and-tied-low ball in the middle of a 'return void' in the
>Stratix II ball grid would have resulted in much of a change for
>Howard's and Mark's results if they were observing package inductive
>coupling effects (would it?)--Howard Johnson said that he determined
>the on-chip decoupling to be nearly ideal in both devices.  Would not
>the circuitous return path through a stuck-hi/low I/O be of little help
>in alleviating inductive coupling of signal I/O?
>
>Based on all of these assumptions, my thought is that if Altera managed
>to improve the on-die decoupling for their Stratix II, the SSN effect
>seen by our other team with the Stratix I may have been addressed in
>Stratix II, and that adding extra driven-and-tied-low I/Os wouldn't
>help any potential SSN problems with Stratix II.
>
>Does my reasoning seem even the slightest bit reasonable?
>
>Thanks,
>-don
>
>P.S.  Your and Scott McMorrow's DesignCon 2005 papers on the Teraspeed
>web site have been very helpful in designing our board-level PDN.  It
>was a great piece of work!
>--
>Don Nelson
>The [United States] Constitution only gives you the right to pursue
>happiness; you have to catch it yourself.  --Ben Franklin
>
>On Mar 4, 2005, at 6:54 AM, steve weir wrote:
>
> > Don, the different tests evaluate different characteristics.
> >
> > While Altera notes a number of measures they have taken to make their
> > offering compelling, there is no free lunch.  I believe that the
> > cross-talk
> > demonstrated by Dr. Johnson's models and experiments done for Xilinx
> > is
> > real,  and is due to the sparse return paths in the I/O fields on the
> > StratixII parts tested.  However, the next question should IMO be:  how
> > much do these differences matter to applications any given user would
> > consider?  Altera notes that Vil even with all signals in a bank
> > switching
> > does not get violated.  What they do not comment on is timing
> > push-out.  We
> > can of course turn that around and apply the same reasoning to the
> > Xilinx
> > test results.
> >
> > We aren't going to get that answer from IBIS models that lack
> > cross-talk
> > effects from the PDN.  ( See one of Chris Cheng's repeated points. )
> > So,
> > while Altera has apparently used a reasonable method to conduct their
> > evaluation, just as Xilinx via Dr. Johnson used reasonable methods in
> > their
> > experiments, they each evaluate separate phenomena.  I do not believe
> > that
> > either test is adequate to draw conclusions on the suitability of
> > either
> > part to a given application.
> >
> > There is probably quite a bit of opportunity here to do some papers
> > that
> > compare what can be done with each part for  a particular type of
> > application, and what has to be done in the external environment to
> > really
> > achieve that performance.
> >
> > Steve.
> >
> > At 12:49 PM 3/3/2005 -0500, Don & Melissa Nelson wrote:
> >> I thought that you all might be interested in reading Altera's
> >> response
> >> to the the recent Xilinx Webinar:
> >> http://www.altera.com/literature/wp/signal-integrity_s2-v4.pdf
> >>
> >> I'm hardly qualified to comment on this, but they do raise some
> >> interesting points.  However, they seem to be limiting their analysis
> >> of Xilinx to simulations (understandable, as Virtex-4s are hard to
> >> come
> >> by right now) and they don't comment on the i/o strength selected for
> >> each device.
> >>
> >> Interestingly, they seem to confirm Xilinx's claim that the ground
> >> bounce can reach 300mV, but note that, for HSTL-II at least, this is
> >> still within the Vil allowance.
> >>
> >> I would be very interested to hear an expert comment on the test
> >> methodology of this paper compared with Xilinx's, which seemed quite
> >> rigorous to my inexperienced eyes.
> >>
> >> cheers,
> >> -don
> >> --
> >> Don Nelson
> >> Sr. Hardware Development Engineer
> >> Marconi Corporation, Plc.
> >> Pittsburgh, PA  15086
> >> (724) 742-6044
> >>
> >> The [United States] Constitution only gives people the right to pursue
> >> happiness; you have to catch it yourself.  --Ben Franklin
> >>
> >>
> >>
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