FreeLists / si-list / [SI-LIST] Re: Paper on BGA crosstalk and power system (Altera Responds)

[steve weir <weirsi@xxxxxxxxxx>]

Don, the different tests evaluate different characteristics.

While Altera notes a number of measures they have taken to make their 
offering compelling, there is no free lunch.  I believe that the cross-talk 
demonstrated by Dr. Johnson's models and experiments done for Xilinx  is 
real,  and is due to the sparse return paths in the I/O fields on the 
StratixII parts tested.  However, the next question should IMO be:  how 
much do these differences matter to applications any given user would 
consider?  Altera notes that Vil even with all signals in a bank switching 
does not get violated.  What they do not comment on is timing push-out.  We 
can of course turn that around and apply the same reasoning to the Xilinx 
test results.

We aren't going to get that answer from IBIS models that lack cross-talk 
effects from the PDN.  ( See one of Chris Cheng's repeated points. )  So, 
while Altera has apparently used a reasonable method to conduct their 
evaluation, just as Xilinx via Dr. Johnson used reasonable methods in their 
experiments, they each evaluate separate phenomena.  I do not believe that 
either test is adequate to draw conclusions on the suitability of either 
part to a given application.

There is probably quite a bit of opportunity here to do some papers that 
compare what can be done with each part for  a particular type of 
application, and what has to be done in the external environment to really 
achieve that performance.

Steve.

At 12:49 PM 3/3/2005 -0500, Don & Melissa Nelson wrote:
>I thought that you all might be interested in reading Altera's response
>to the the recent Xilinx Webinar:
>http://www.altera.com/literature/wp/signal-integrity_s2-v4.pdf
>
>I'm hardly qualified to comment on this, but they do raise some
>interesting points.  However, they seem to be limiting their analysis
>of Xilinx to simulations (understandable, as Virtex-4s are hard to come
>by right now) and they don't comment on the i/o strength selected for
>each device.
>
>Interestingly, they seem to confirm Xilinx's claim that the ground
>bounce can reach 300mV, but note that, for HSTL-II at least, this is
>still within the Vil allowance.
>
>I would be very interested to hear an expert comment on the test
>methodology of this paper compared with Xilinx's, which seemed quite
>rigorous to my inexperienced eyes.
>
>cheers,
>-don
>--
>Don Nelson
>Sr. Hardware Development Engineer
>Marconi Corporation, Plc.
>Pittsburgh, PA  15086
>(724) 742-6044
>
>The [United States] Constitution only gives people the right to pursue
>happiness; you have to catch it yourself.  --Ben Franklin
>
>
>
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