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[SI-LIST] Paper on BGA crosstalk and power system (Altera Responds)
- From: Don & Melissa Nelson <dhwn@xxxxxxx>
- To: SI List <si-list@xxxxxxxxxxxxx>
- Date: Thu, 3 Mar 2005 12:49:52 -0500
I thought that you all might be interested in reading Altera's response
to the the recent Xilinx Webinar:
http://www.altera.com/literature/wp/signal-integrity_s2-v4.pdf
I'm hardly qualified to comment on this, but they do raise some
interesting points. However, they seem to be limiting their analysis
of Xilinx to simulations (understandable, as Virtex-4s are hard to come
by right now) and they don't comment on the i/o strength selected for
each device.
Interestingly, they seem to confirm Xilinx's claim that the ground
bounce can reach 300mV, but note that, for HSTL-II at least, this is
still within the Vil allowance.
I would be very interested to hear an expert comment on the test
methodology of this paper compared with Xilinx's, which seemed quite
rigorous to my inexperienced eyes.
cheers,
-don
--
Don Nelson
Sr. Hardware Development Engineer
Marconi Corporation, Plc.
Pittsburgh, PA 15086
(724) 742-6044
The [United States] Constitution only gives people the right to pursue
happiness; you have to catch it yourself. --Ben Franklin
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