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[SI-LIST] Re: Paper on BGA crosstalk and power system

  • From: tcronin@xxxxxxxxxx
  • To: <ludwig@xxxxxxxxxxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
  • Date: Thu, 3 Mar 2005 09:22:03 -0600
Mark & Howard,
        I saw the presentation, but was unable to stay through the Q & A
portion.  All-in-all I thought that the presentation was good.  Well
done Howard and Mark.
Cliff & Steve, et al  
        What about choosing a different I/O standard altogether?  I've
used Xilinx FPGA's; I haven't used Altera's devices in the past.  I have
to admit that I don't really know for certain that the edge
characteristics would match any better.  
From the Altera website I see that the Stratix 2 parts support the
following I/O standards:
"LVTTL, LVCMOS, SSTL, HSTL, GTL+, CTT, AGP, LVDS, LVPECL, PCML,
HyperTransport, SSTL-2, SSTL-3, SSTL-18, HSTL Class I & II, PCI, PCI-X,
Differential SSTL, Differential HSTL "

From the Xilinx website I see that the Virtex 4 parts support the
following I/O standards:
"Single-ended electrical standard support for LVTTL, LVCMOS (3.3V, 2.5V,
1.8V, and 1.5V), PCI (33 and 66 MHz), PCI-X, GTL and GTL+, HSTL 1.5V and
1.8V (Class I, II, III, and IV), and SSTL 2.5V and 1.8V (Class I and
II). 
Differential electrical standard support for 840 LVDS, Extended LVDS
(2.5V), Bus LVDS, ULVDS, LVPECL 2.5V, and HyperTransport (LDT). All I/Os
can be configured as differential I/O without any placement restriction
for flexibility. "

If I'm missing any of the I/O standards supported for either device
family, I apologize for not being able to take the time to really go
through either website. 

Terry Cronin

-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Stefan Ludwig
Sent: Thursday, March 03, 2005 8:36 AM
To: SI List
Cc: clifford@xxxxxxxxxxxxx; weirsi@xxxxxxxxxx
Subject: [SI-LIST] Re: Paper on BGA crosstalk and power system

Hi Cliff & Steve,

I have seen the webcast and in that, Dr. Johnson mentioned that Altera 
didn't have a fast vs. slow setting for the slew rate. Therefore, they 
used fast on Xilinx, but had to live with the even faster edge rate of 
Altera's devices.

Maybe a fairer comparison would have been 8mA A vs. 12mA X, i.e., 
compensate faster slew rate of A with higher drive strength of X, but 
I'm not sure that would have yielded a comparable result.

Just my opinion.

Stefan

Clifford van Dyk wrote:

>Hi Mark
>A very interesting paper indeed. While not having seen the webcast, I 
>assume that the content is more or less contained within the paper. 
>While I do not see myself in the same league as other S.I. experts in 
>the forum, hopefully my opinion is in some way useful. I would be 
>interested to know the following:
>
>The final simulations show what looks to me like a 6 time greater 
>crosstalk in the Altera package. This was done under the assumption
that 
>di/dt was the same for both devices. The measured results (a ratio of 
>4.5:1) were made with the Altera drivers being significantly stronger 
>than the Xilinx drivers. I would therefore have expected the simulated 
>ratio to be less that 4.5:1, rather than the ca. 6:1 that seems to be 
>indicated on figure 21. Why do you think this discrepancy exists?
>
>Also, it may have been more useful to perform the origional
measurements 
>with equivalent drive strengths (measured risetimes, rather than "8mA" 
>vs. "8mA fast", which was by your own admission, misleading) to get a 
>more apples-to-apples measurement. Do you agree?
>
>Nevertheless, very interesting! Thank you for sharing.
>
>Kind regards,
>Clifford
>
>Mark Alexander wrote:
>
>  
>
>>Hey all,
>>Some of you may have already attended this, but I wanted to draw your 
>>attention to a WebCast seminar and accompanying paper that was
released 
>>yesterday.  The topic is a joint study by Xilinx and SigCon (Howard 
>>Johnson) of crosstalk and power system noise in FPGA systems.
>>
>>The paper:
>>http://www.xilinx.com/products/virtex4/pdfs/BGA_Crosstalk.pdf
>>
>>The archived WebCast (might not be available until tomorrow):
>>http://www.xilinx.com/events/webcasts/tol/01feb05.htm#3
>>
>>The WebCast is a full hour with Q&A at the end; the paper /seems /long

>>but is actually pretty easy to read.  I especially like Howard's 
>>explanation of the crosstalk model of power system noise and why it's 
>>appropriate to the large BGA scenario.
>>
>>I'd be very interested to hear feedback from people on the list -- 
>>factors we didn't consider, overall usefulness of the information 
>>presented, ideas for future studies on the same measurement platform. 
>>
>>Thanks!
>>mark
>>
>>
>>
>>
>> 
>>
>>    
>>
>
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-- 

Ludwig Systems Engineering         Consulting - Design - Implementation
WWW: www.ludwigsystems.com         System Architectures - FPGAs - PCBs
Ph/Fx: +41-43-355-58-73/74         Hardware - Firmware - Software

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