FreeLists / si-list / [SI-LIST] Re: Controlled Impedance Coupon Design

["Scott McMorrow" <scott@xxxxxxxxxxxxx>]

Steve,

Good comments.  

It is easy to define the delay of a pure sine wave and easy to measure 
with the right equipment.  As for a pulse, this begs the question, what 
is the shape of the pulse and where on the pulse do you care to measure 
the delay from and to?

Delay is really a secondary measurement which depends upon the material 
properties of the dielectric and conductors, along with the geometry of 
the conductors. (Geometry is important because of the losses within the 
conductor due to finite field penetration into the material.) It also 
varies with frequency and/or pulse shape. What might better be required 
is a way to measure the primary material properties of Er, Conductivity, 
and surface roughness.

Both are pretty much beyond the scope of a simple TDR test trace.

----------------------------- segue into complaint section 
----------------------------------------

As a segue into a related topic, I shake my head when semiconductor 
vendors provide bus design guidelines that require trace matching within 
+/- 10 mils on an FR4 substrate.  (Yes, I did see this specification in 
a recent design guideline.) This is equivalent to saying that delay must 
be matched to within 1.8 ps (give or take a few friendly femtoseconds.) 
 I can spit on a microstrip trace and see much greater delay than that. 
Variations in via pad and antipad dimensions, along with registration, 
will cause greater delay than that.  And must I mention that with woven 
materials (like FR4) routing directionality will cause greater delay 
than that.  Oh, and has anyone looked at the routing in the packages 
these guys are using.  A package plating tail will introduce delays that 
vary with frequency and neighbor tail coupling.

What are they thinking?
----------------------------- end of complaint section 
----------------------------------------


best regards,

scott


-- 
Scott McMorrow
Teraspeed Consulting Group LLC
2926 SE Yamhill St.
Portland, OR 97214
(503) 239-5536
http://www.teraspeed.com



Steve Corey wrote:

>Ed -- Your point is a good one -- that there is uncertainty involved in 
>measuring (actually in defining) delay.  That is, prior to measuring 
>delay, you have to define what delay you are measuring.  However, I 
>don't think the issue you raise can be resolved by changing domains.
>
>In the presence of loss, delay is frequency dependent.  Or equivalently, 
>as you have mentioned, the delay you measure in the time domain depends 
>on what voltage level you choose for your measurements.  These 
>uncertainties are intrinsic to the problem, and not specific to the 
>domain you choose for your measurements.
>
>More precisely, the issue is not measurement accuracy as much as 
>definition.  There is ambiguity in the assumption that there exists a 
>single number for delay which is independent of signal shape.  Once you 
>step away from an ideal lossless transmission line, delay is dependent 
>on signal shape.  This is a second order effect in typical digital 
>design usage, but it's present in either domain.
>
>For this reason, we advise our customers who are doing digital design to 
>measure delay using signals that are as close as possible to the ones 
>they will be using in practice.  This means taking the measurement in 
>the time domain, and filtering the signals if appropriate.  The time 
>domain delay is effectively a weighted averaging of all the 
>frequency dependent delays together, and the weighting system it uses is 
>defined by the shape (i.e., the "frequency content") of the signal.  To 
>be rigorous, the voltage levels you use to measure delay in the time 
>domain should also have relevance to the signaling scheme for which you 
>are designing.
>
>I realize that such an application specific delay measurement is of 
>limited use in defining standards, which is why this thread started in 
>the first place.  With respect to standards, the point is that by 
>choosing a specific measurement technique which yields a single value 
>for delay, you have essentially chosen one definition of delay from an 
>infinite number of available definitions.  Repeatability is important, 
>but since people will be using this number to solve specific problems, 
>the key question is how this number relates to the problems they are 
>trying to solve.
>
>   -- Steve
>
>-------------------------------------------
>Steven D. Corey, Ph.D.
>Time Domain Analysis Systems, Inc.
>"The Interconnect Modeling Company."
>http://www.tdasystems.com
>
>email: steven.corey@xxxxxxxxxxxxxx
>phone: (503) 246-2272
>fax:   (503) 246-2282
>-------------------------------------------
>
>
>Ed Priest wrote:
>
>  
>
>>A neat trick I've used to measure the propagation delay. Instead of
>>trying to pick off the delay from a TDR (you always have some accuracy
>>issues with picking the starting and ending points) is to build a test
>>stub.
>>
>>                      |
>>                      |
>>                      |
>>   C ---------------------------------- C
>>
>>Look at S21 between the two connectors and the frequency distance
>>between the minimums will be the 1/2 wavelength. It's an easy relative
>>measurement to pick off the curve. Even without a VNA - a simple
>>frequency sweep provides very accurate results.
>>
>>Ed
>>
>>-----Original Message-----
>>From: Ken Willis [mailto:kwillis@xxxxxxxxxxx]=20
>>Sent: Thursday, March 06, 2003 8:50 AM
>>To: brian.butler@xxxxxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
>>Subject: [SI-LIST] Re: Controlled Impedance Coupon Design
>>
>>
>>H Brian
>>
>>Besides impedance, another critical aspect is the prop delay
>>characteristics per layer. This gets really important whey you
>>are trying to control skew between clock and data lines to 10's
>>of picoseconds. The impedance coupons could help a lot if, instead
>>of all the test lines on a layer just being a standard 6" length,
>>there was an additional line that was a different known length
>>on each layer. For example if there were an additional test line
>>4 inches long, then the engineer could figure out with a TDR the prop
>>delay/inch for the various layers, and could more accurately design
>>the skew offsets into the layout. I think this will be more and more
>>important as we go along to higher speeds. This idea has been proposed
>>on the SI-list more than once. I'm sure people are doing this on their
>>own today, as I have done in the past.
>>
>>Ken=3D20
>>
>>-----Original Message-----
>>From: Brian Butler [mailto:brian.butler@xxxxxxxxxxxxxxx]=3D20
>>Sent: Tuesday, March 04, 2003 11:28 AM
>>To: si-list@xxxxxxxxxxxxx
>>Subject: [SI-LIST] Controlled Impedance Coupon Design
>>
>>To All:
>>
>>The IPC task group which is rewriting the IPC-2141 Controlled Impedance
>>=3D
>>Circuit
>>Boards and High Speed Logic Design is looking into the need of rewriting
>>=3D
>>the
>>Controlled Impedance Coupon Design Rules (Section 4.7 of current =3D
>>document) and
>>would welcome your input on the following issues concerning controlled
>>impedance coupon design. Please feel free to comment on any or all of =
>>=3D
>>the below
>>listed points.
>>
>>Potential Topics for Controlled Impedance Design Rules
>>
>>1)      Terminate or un-terminated traces?
>>2)      Test points are plated thru holes?
>>3)      Size of Drilled Hole?
>>4)      Size of pad?
>>5)      Single-ended pitch between signal and ground?
>>6)      Differential pitch and pattern?
>>7)      Differential pattern (no ground reference, one ground reference,
>>=3D
>>two
>>ground references)?
>>8)      Width of coupon?
>>9)      Length of test trace?
>>10)     Use of thieving?
>>11)     Need for consistent orientation of probe pads to eliminate the =
>>=3D
>>need for
>>test operators to rotate the probe (repetitive stress)?
>>12)     Bends in trace or no allowed bends?
>>13)     Minimum spacing from one test structure to the next?
>>14)     Type of nomenclature and clearance specifications?
>>15)     Tie all ground/power planes together on coupon?
>>16)     Ideal location of coupon(s) on panel?
>>17)     Square lands to identify grounds/power reference points?
>>18)     Other issues?
>>
>>
>>
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>
>
>  
>



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