Date Index for si-list, 03-2003

[si-list] || [03-2003 Date Index] [03-2003 Thread Index]

[SI-LIST] Re: 8b/10b program using MATLAB - Rotem Gazit
[SI-LIST] Request some information about renting SPECCTRAQuest Products . - Farzad Ebrahimi
[SI-LIST] Re: how to simulate with S parameters - Hassan O. Ali
[SI-LIST] Agenda (revised) , European IBIS Summit DATe 2003/Munich - Ralf Bruening
[SI-LIST] Re: how to simulate with S parameters - sam . sim
[SI-LIST] SI Guru - Cleland-Horn, Teresa
[SI-LIST] Re: how to simulate with S parameters - Hassan O. Ali
[SI-LIST] Canbus EMC/SI questions? - Javier del Valle
[SI-LIST] Decoupling a IC - Juan Manuel
[SI-LIST] Re: how to simulate with S parameters - Dohn V. Salvador
[SI-LIST] Meeting Announcement: Silicon Valley Chapter - IPC Designers Council (March 11) - Bob McCreight
[SI-LIST] Meeting Announcement: Silicon Valley Chapter - IPC Designers Council (March 11) - Bob McCreight
[SI-LIST] Re: how to simulate with S parameters - Jian X. Zheng
[SI-LIST] Re: how to simulate with S parameters - Ray Anderson
[SI-LIST] 2.5GB/s data rate connector - Bob Patel
[SI-LIST] Re: 2.5GB/s data rate connector - Michael Khusid
[SI-LIST] Re: Canbus EMC/SI questions? - steve weir
[SI-LIST] Re: 2.5GB/s data rate connector - Al Owens
[SI-LIST] Re: 2.5GB/s data rate connector - Scott McMorrow
[SI-LIST] Re: 2.5GB/s data rate connector - Bergey, Dana
[SI-LIST] Plated through hole capacitance - Fitzgerald, Kevin
[SI-LIST] Re: Plated through hole capacitance - Scott McMorrow
[SI-LIST] Hot Swapping for -5V - hariharan
[SI-LIST] NRZ signaling - sunil-chandra . kasanyal
[SI-LIST] Re: Decoupling a IC - istvan novak
[SI-LIST] Re: NRZ signaling - steve weir
[SI-LIST] Re: NRZ signaling - herbert_lage
[SI-LIST] Re: NRZ signaling - Clewell, Craig
[SI-LIST] Re: NRZ signaling - herbert_lage
[SI-LIST] Re: Hspice diff sim - Bi Han
[SI-LIST] Re: Hspice diff sim - Scott McMorrow
[SI-LIST] Re: NRZ signaling - Mike Brown
[SI-LIST] measurement error - Doug Smith
[SI-LIST] Unlock the power of your backplane, LVDS tutorial - Eitan k
[SI-LIST] Differential signaling history - Zhou, Xingling (Mick)
[SI-LIST] Re: Differential signaling history - Jim G Roberts
[SI-LIST] Re: Differential signaling history - Ingraham, Andrew
[SI-LIST] Re: Differential signaling history - Zhou, Xingling (Mick)
[SI-LIST] Re: Differential signaling history - Zhou, Xingling (Mick)
[SI-LIST] Re: Differential signaling history - George R. Hare/AT-Austin/3M/US
[SI-LIST] Re: Differential signaling history - Charles Hill
[SI-LIST] Re: Differential signaling history - Ingraham, Andrew
[SI-LIST] Modeling a MUX/DEMUX? - Aspnes, Brian D
[SI-LIST] Re: Modeling a MUX/DEMUX? - Jon Powell
[SI-LIST] Re: Modeling a MUX/DEMUX? - Scott McMorrow
[SI-LIST] Re: Modeling a MUX/DEMUX? - Scott McMorrow
[SI-LIST] Re: Modeling a MUX/DEMUX? - Geoff Parker
[SI-LIST] Skin Effect Calculation - Pat Diao
[SI-LIST] JEDEX Workshops on IBIS - Lynne Green
[SI-LIST] Re: Skin Effect Calculation - Bi Han
[SI-LIST] Unlock the power of your backplane, LVDS tutorial (now with the link) - Eitan k
[SI-LIST] Re: Controlled Impedance Coupon Design - Ken Willis
[SI-LIST] Re: Loss Tangent of Solder Mask - Fasig, Jonathan L.
[SI-LIST] Re: Controlled Impedance Coupon Design - Ed Priest
[SI-LIST] Re: Controlled Impedance Coupon Design - Paul Levin
[SI-LIST] Re: Controlled Impedance Coupon Design - Ed Priest
[SI-LIST] Re: Loss Tangent of Solder Mask - ray_waugh
[SI-LIST] Re: Loss Tangent of Solder Mask - Neeraj Pendse
[SI-LIST] Re: simulating Mos in series - Parthasarathy Sampath
[SI-LIST] Re: Loss Tangent of Solder Mask - ray_waugh
[SI-LIST] Re: simulating Mos in series - super cop
[SI-LIST] how to calculate board area & stack - mbestha
[SI-LIST] Re: Loss Tangent of Solder Mask - Scott McMorrow
[SI-LIST] Modelling of Microwave Testing Microprobe (Cascade) - Bi Han
[SI-LIST] is there any hspice to pspice convertor ? - Nimish Aggarwal
[SI-LIST] Instruments / Methods for measuring a cable's characteristic impedance - Peter Baxter
[SI-LIST] Inductance variation. - GEORGE VARGHESE
[SI-LIST] Re: Inductance variation. - Gaurav Agrawal
[SI-LIST] Re: Inductance variation. - Bi Han
[SI-LIST] Re: Inductance variation. - Steve Rogers
[SI-LIST] Re: Inductance variation. - Rich Peyton
[SI-LIST] Re: Inductance variation. - boris . traa
[SI-LIST] Re: is there any hspice to pspice convertor ? - Clewell, Craig
[SI-LIST] Re: is there any hspice to pspice convertor ? - ZL e-Studio
[SI-LIST] Re: is there any hspice to pspice convertor ? - Clewell, Craig
[SI-LIST] Re: how to calculate board area & stack - Paul Taddonio
[SI-LIST] Re: Instruments / Methods for measuring a cable'schara cteristic impedance - James_R_Jones
[SI-LIST] Re: Loss Tangent of Solder Mask - Jim DeLap
[SI-LIST] Re: Loss Tangent of Solder Mask - Eric Sweetman
[SI-LIST] Re: Loss Tangent of Solder Mask - Swanson, Dan
[SI-LIST] Re: Loss Tangent of Solder Mask - Jim G Roberts
[SI-LIST] Re: Loss Tangent of Solder Mask - bpanos
[SI-LIST] Re: Instruments / Methods for measuring a cable's chara cteristic impedance - Tom Dagostino
[SI-LIST] Re: Loss Tangent of Solder Mask - Scott McMorrow
[SI-LIST] Re: Instruments / Methods for measuring a cable's characteristic impedance - Paul Levin
[SI-LIST] Re: Loss Tangent of Solder Mask - gustavo . duenas
[SI-LIST] Re: Loss Tangent of Solder Mask - Michael Khusid
[SI-LIST] Re: Loss Tangent of Solder Mask - Scott McMorrow
[SI-LIST] Re: Loss Tangent of Solder Mask - Scott McMorrow
[SI-LIST] Re: question about IBIS's V-T curve Scaling ? - Muranyi, Arpad
[SI-LIST] Re: Controlled Impedance Coupon Design - Steve Corey
[SI-LIST] Needed Manager "SI" - Zeiger and Associates LLC
[SI-LIST] Re: Controlled Impedance Coupon Design - Scott McMorrow
[SI-LIST] Re: Coupling THROUGH a plane? - Boris Yost
[SI-LIST] Re: Coupling THROUGH a plane? - Scott McMorrow
[SI-LIST] Re: Controlled Impedance Coupon Design - Volk, Andrew M
[SI-LIST] Re: Needed Manager "SI" - Ray Anderson
[SI-LIST] Re: Loss Tangent of Solder Mask - Neeraj Pendse
[SI-LIST] Length matching of source synchronous busses. - Scott McMorrow
[SI-LIST] Re: Loss Tangent of Solder Mask - Scott McMorrow
[SI-LIST] Re: Length matching of source synchronous busses. - Jeremy Plunkett
[SI-LIST] Re: Instruments / Methods for measuring a cable's chara cteristic impedance - john lipsius
[SI-LIST] Couple increased or decreased? (transmission line on silicon die) - Bi Han
[SI-LIST] Re: Length matching of source synchronous busses. - Scott McMorrow
[SI-LIST] Crossing thick traces - Alex Horvath
[SI-LIST] Re: Instruments / Methods for measuring a cable's chara cteristic impedance - Tom Dagostino
[SI-LIST] Re: Length matching of source synchronous busses. - Sparkman, Aubrey
[SI-LIST] Re: Length matching of source synchronous busses. - john lipsius
[SI-LIST] IEEE Presentation download - Charles Grasso
[SI-LIST] Re: Couple increased or decreased? (transmission line on silicon die) - Raymond . Leung
[SI-LIST] (No Subject) - GEORGE VARGHESE
[SI-LIST] (No Subject) - GEORGE VARGHESE
[SI-LIST] High speed diff. lines connector - Edi Fraiman
[SI-LIST] Re: High speed diff. lines connector - steve weir
[SI-LIST] Availability of IBIS models - Gaurav Agrawal
[SI-LIST] contact ESD - Russel Hughes
[SI-LIST] Re: Length matching of source synchronous busses. - Ken Cantrell
[SI-LIST] Re: contact ESD - npischl
[SI-LIST] Sigrity seeks Applications Engineer - Teo Yatman
[SI-LIST] Re: Length matching of source synchronous busses. - Jerry Martinson
[SI-LIST] Re: Length matching of source synchronous busses. - Scott McMorrow
[SI-LIST] Re: Couple increased or decreased? (transmission line on silicon die) - D G
[SI-LIST] Re: Couple increased or decreased? (transmission line on silicon die) - Bi Han
[SI-LIST] Re: Length matching of source synchronous busses. - Jeremy Plunkett
[SI-LIST] Re: Length matching of source synchronous busses. - Jeremy Plunkett
[SI-LIST] Bazooka balun verification. - GEORGE VARGHESE
[SI-LIST] Re: Length matching of source synchronous busses. - Robert Haller
[SI-LIST] Analog/Digital Gnd - Parthasarathy Sampath
[SI-LIST] Re: Analog/Digital Gnd - James_R_Jones
[SI-LIST] Re: Analog/Digital Gnd - steve weir
[SI-LIST] Re: Analog/Digital Gnd - Juergen Hannappel
[SI-LIST] Re: Analog/Digital Gnd - Michael Khusid
[SI-LIST] Re: Analog/Digital Gnd - James_R_Jones
[SI-LIST] Re: Analog/Digital Gnd - San Miguel, Shane
[SI-LIST] Re: Analog/Digital Gnd - steve weir
[SI-LIST] Single-ended S-para plot of 2 microstrip traces - sam . sim
[SI-LIST] Re: Single-ended S-para plot of 2 microstrip traces - Jian X. Zheng
[SI-LIST] Re: Single-ended S-para plot of 2 microstrip traces - Scott McMorrow
[SI-LIST] Re: Single-ended S-para plot of 2 microstrip traces - Loyer, Jeff
[SI-LIST] Re: Couple increased or decreased? (transmission line on silicon die) - Raymond . Leung
[SI-LIST] Re: Single-ended S-para plot of 2 microstrip traces - Paul Levin
[SI-LIST] Re: Single-ended S-para plot of 2 microstrip traces - Bi Han
[SI-LIST] Re: Analog/Digital Gnd - hariharan
[SI-LIST] Re: Analog/Digital Gnd - steve weir
[SI-LIST] Re: Analog/Digital Gnd - Jack Stone
[SI-LIST] Re: Analog/Digital Gnd - Chetan Jadhav
[SI-LIST] Re: Analog/Digital Gnd - Jack Stone
[SI-LIST] Re: Length matching of source synchronous busses. - Jon Powell
[SI-LIST] Series termination - Edi Fraiman
[SI-LIST] Re: Series termination - Scott McMorrow
[SI-LIST] Re: Length matching of source synchronous busses. - Scott McMorrow
[SI-LIST] Re: Series termination - Hofmann, Mark
[SI-LIST] Re: Series termination - Ingraham, Andrew
[SI-LIST] Zo vs Zin - Jayaprakash Balachandran
[SI-LIST] Re: Zo vs Zin - Clewell, Craig
[SI-LIST] Re: Series termination - Bill Reams
[SI-LIST] Re: Zo vs Zin - GEORGE VARGHESE
[SI-LIST] Re: Analog/Digital Gnd - steve weir
[SI-LIST] Re: Length matching of source synchronous busses. - steve weir
[SI-LIST] A presentation and more - Issa, Elie
[SI-LIST] Re: A presentation and more - Rich Peyton
[SI-LIST] Re: Series termination - Tom Biggs
[SI-LIST] Please Urgent - mmirfan
[SI-LIST] Re: Please Urgent - Bill Beale
[SI-LIST] Re: Series termination - steve weir
[SI-LIST] Available SI engineering position - Simon Assouad
[SI-LIST] Re: Please Urgent - Ray Anderson
[SI-LIST] Re: Series termination - Ed Sayre III
[SI-LIST] Re: A presentation and more - Faisal Baloch
[SI-LIST] Re: [IS-LIST] Please Urgent - Robert Kezer
[SI-LIST] Re: [IS-LIST] Please Urgent - John L. Prince
[SI-LIST] Re: [IS-LIST] Please Urgent - Knighten, Jim L
[SI-LIST] Re: [IS-LIST] Please Urgent - Youssef Khalife
[SI-LIST] Re: [IS-LIST] Please Urgent - Matthias Mansfeld
[SI-LIST] Re: [IS-LIST] Please Urgent - Ray Anderson
[SI-LIST] Re: Analog/Digital Gnd - Bart Bouma
[SI-LIST] Re: Series termination - Jack Stone
[SI-LIST] Setting up Spectraquest to report capacitance for package design - Suk Hui Teh
[SI-LIST] NEED PCB PRODUCED WITH BLIND & BURIED VIAS ? - Steve Rogers
[SI-LIST] Re: Zo vs Zin - Om Mandhana
[SI-LIST] Re: Zo vs Zin - Zhou, Xingling (Mick)
[SI-LIST] Re: Zo vs Zin - Loyer, Jeff
[SI-LIST] Re: A presentation and more - Issa, Elie
[SI-LIST] Re: Analog/Digital Gnd - Ron Miller
[SI-LIST] DDR Module A13 Pin Location - Jay Daugherty
[SI-LIST] Power Consumption of a bus - Lucas Bossetti
[SI-LIST] Re: Power Consumption of a bus - John Lin (???)
[SI-LIST] Re: Power Consumption of a bus - steve weir
[SI-LIST] Re: Power Consumption of a bus - Lucas Bossetti
[SI-LIST] Connectors and PECL terminations - hariharan
[SI-LIST] Buried Vias and microvias - Juan Manuel
[SI-LIST] Loss in HSPICE W Element - Timothy Coyle
[SI-LIST] Re: Loss in HSPICE W Element - Alain Everaert
[SI-LIST] Problem with Ni plated transmission line - Daniel Kuchta
[SI-LIST] Measuring 0.13micron CMOS devices - srinivasan
[SI-LIST] Re: Measuring 0.13micron CMOS devices - Stuart Brorson
[SI-LIST] Fw: Problem with Ni plated transmission line - Daniel Kuchta
[SI-LIST] Re: Measuring 0.13micron CMOS devices - San Miguel, Shane
[SI-LIST] Re: Power Consumption of a bus - Ken Cantrell
[SI-LIST] Re: NEED PCB PRODUCED WITH BLIND & BURIED VIAS ? - SMITH, Andy (STV)
[SI-LIST] Re: Power Consumption of a bus - Ingraham, Andrew
[SI-LIST] Re: Fw: Problem with Ni plated transmission line - Aubrey_Sparkman
[SI-LIST] Fw: Problem with Ni plated transmission line - Daniel Kuchta
[SI-LIST] Re: Power Consumption of a bus - steve weir
[SI-LIST] Fw: Re: Fw: Problem with Ni plated transmission line - Daniel Kuchta
[SI-LIST] Re: Problem with Ni plated transmission line - Beal, Weston
[SI-LIST] Re: Buried Vias and microvias - Abe Riazi
[SI-LIST] Re: Fw: Re: Fw: Problem with Ni plated transmission line - Issa, Elie
[SI-LIST] Re: Problem with Ni plated transmission line - Richard Wheeler
[SI-LIST] Re: Problem with Ni plated transmission line - Daniel Kuchta
[SI-LIST] Re: Fw: Problem with Ni plated transmission line - Chris Schmolze
[SI-LIST] Re: Fw: Re: Fw: Problem with Ni plated transmission line - John Barnes
[SI-LIST] Carlsbad, CA High Speed Design for PCB Designers: Routing and Terminating High Speed - Lori Lesnick
[SI-LIST] Re: Fw: Problem with Ni plated transmission line - Matthew Herndon
[SI-LIST] Measuring 1G+ signals - Alex Horvath
[SI-LIST] Re: Loss in HSPICE W Element - Alex Horvath
[SI-LIST] Re: Loss in HSPICE W Element - Gong Haifeng (Bill)
[SI-LIST] [SI-LIST]Re: Problem with Ni plated transmission line - Issa, Elie
[SI-LIST] Re: Zo vs Zin - Muranyi, Arpad
[SI-LIST] Re: Zo vs Zin - Jayaprakash Balachandran
[SI-LIST] Re: Signal Integrity and Zeiger - Grasso, Charles
[SI-LIST] Re: Zo vs Zin - Beal, Weston
[SI-LIST] Re: A presentation and more - Issa, Elie
[SI-LIST] Re: Signal Integrity and Zeiger - Russel Hughes
[SI-LIST] S, ABCD and T parameters - Ray Anderson
[SI-LIST] Re: S, ABCD and T parameters - Kyung Suk (Dan) Oh
[SI-LIST] SI conference/workshop in Germany? - Michael Khusid
[SI-LIST] Re: SI conference/workshop in Germany? - Ji Zheng
[SI-LIST] Re: S, ABCD and T parameters - Luca Giacotto
[SI-LIST] Re: SI conference/workshop in Germany? - Muranyi, Arpad
[SI-LIST] Signal Integrity Contract - Janos Gaspar
[SI-LIST] Re: S, ABCD and T parameters - Ege Engin
[SI-LIST] low noise oscillators - C Deibele
[SI-LIST] Two requests - Doug Brooks
[SI-LIST] Re: Two requests - Kim Helliwell
[SI-LIST] Re: Two requests - Swanson, Dan
[SI-LIST] Re: Two requests - Beal, Weston
[SI-LIST] Re: Two requests - Bill Reams
[SI-LIST] Re: Two requests - John Coupland
[SI-LIST] Re: Two requests - Feldman, Richard
[SI-LIST] Re: Two requests - Bob Drzyzgula
[SI-LIST] Re: Two requests - ray_waugh
[SI-LIST] Re: Two requests - Fred Townsend
[SI-LIST] Re: Fw: Problem with Ni plated transmission line - Neeraj Pendse
[SI-LIST] One question left!!!!! - Doug Brooks
[SI-LIST] Re: Two requests - Loyer, Jeff
[SI-LIST] which is load and source treated - mbestha
[SI-LIST] Re: One question left!!!!! - Paul Levin
[SI-LIST] Re: Two requests - Bart Bouma
[SI-LIST] Re: One question left!!!!! - Ross_Amans
[SI-LIST] Power plane thickness tolerance - Kon, Hon Lee
[SI-LIST] Trace width and current capacity - Harjeet Singh Randhawa
[SI-LIST] Flat Flex Cable Impedance - Christopher . Crowley
[SI-LIST] Re: Power plane thickness tolerance - John Barnes
[SI-LIST] Re: Flat Flex Cable Impedance - Julian Ferry
[SI-LIST] Re: Flat Flex Cable Impedance - Ray Anderson
[SI-LIST] Re: Flat Flex Cable Impedance - Hal Murray
[SI-LIST] Re: Trace width and current capacity - Harry Selfridge
[SI-LIST] Question on Impedance Control - Pat Diao
[SI-LIST] Re: Question on Impedance Control - Bill Beale
[SI-LIST] Re: Question on Impedance Control - Zabinski, Patrick J.
[SI-LIST] Re: Flat Flex Cable Impedance - Julian Ferry
[SI-LIST] SI - VHDL - susanli_ucla
[SI-LIST] Re: Two requests - Muranyi, Arpad
[SI-LIST] Re: Two requests - Larry Barnes
[SI-LIST] Re: Question on Impedance Control - Nirmal Sharma
[SI-LIST] Re: Two requests - Bill Reams
[SI-LIST] Re: Two requests - Sandor Daranyi
[SI-LIST] Re: Flat Flex Cable Impedance - k EPD
[SI-LIST] Re: Flat Flex Cable Impedance - Ravinder Ajmani
[SI-LIST] Doping effects. - GEORGE VARGHESE
[SI-LIST] Re: Doping effects. - Teh Lip Khoon
[SI-LIST] Re: Two requests - Bart Bouma
[SI-LIST] Re: Two requests - Brian Martin
[SI-LIST] Looking for RF job in Canada - Steve Rogers
[SI-LIST] Re: Doping effects. - GEORGE VARGHESE
[SI-LIST] current rating of wirebonds - Jan Vercammen
[SI-LIST] which is the Best routing Topology - Sudheer B S
[SI-LIST] Re: Trace width and current capacity - John Barnes
[SI-LIST] Re: current rating of wirebonds - John Barnes
[SI-LIST] Re: Doping effects. - Ed Sayre III
[SI-LIST] Re: Trace width and current capacity - Jim Roberts
[SI-LIST] current rating of wirebonds - Jan Vercammen
[SI-LIST] Re: Question on Impedance Control - Larry Barnes
[SI-LIST] Re: Doping effects. - Tabatchnick, Justin
[SI-LIST] Re: Doping effects. - Ed Sayre III
[SI-LIST] Flat Flex Cable Impedance - Measurement - Peter Baxter
[SI-LIST] Re: Series termination - Piyush Gupta
[SI-LIST] Ground setting in ADS of Agilent - Zhou Jinchang
[SI-LIST] How to model Output buffer with feedback in IBIS? - Yehuda Yizraeli
[SI-LIST] Re: How to model Output buffer with feedback in IBIS? - Tom Dagostino
[SI-LIST] How to locate Lambda-Refine Mesh in HFSS? - Shi, Wenjunx
[SI-LIST] how to model connectors - mbestha
[SI-LIST] Printed Resistors - Steve Rogers
[SI-LIST] Re: How to model Output buffer with feedback in IBIS? - Jon Powell
[SI-LIST] Re: how to model connectors - Jon Powell
[SI-LIST] Reflections for dummies - San Miguel, Shane
[SI-LIST] Re: Reflections for dummies - e.sweetman
[SI-LIST] hspice model for Giga Ethernet Tx/Rx - Guasti Giovanni
[SI-LIST] PCI Edge connector - Sankar karuppannan
[SI-LIST] Re: Reflections for dummies - Jon Powell
[SI-LIST] Re: PCI Edge connector - Ivor Bowden
[SI-LIST] Re: PCI Edge connector - Michael Khusid
[SI-LIST] SI/EMC Job Openings - 설병수
[SI-LIST] How to Zigzag trace! - peter zhu
[SI-LIST] Fwd: Comparison between Raphael and Hspice - Sudha Thiru
[SI-LIST] ask for comments on high frequency filter design - Wei Zhang
[SI-LIST] Job Opportunity - jeremy hillcrest
[SI-LIST] ePlanner(Scratchpad)/XTK from Innoveda - Aspnes, Brian D
[SI-LIST] Re: Coax vs. Microstrip - ray_waugh
[SI-LIST] Re: Coax vs. Microstrip - Scott McMorrow
[SI-LIST] Re: ePlanner(Scratchpad)/XTK from Innoveda - Alan Hilton-Nickel
[SI-LIST] Re: ePlanner(Scratchpad)/XTK from Innoveda - Geoff Parker
[SI-LIST] Re: ePlanner(Scratchpad)/XTK from Innoveda - Tadashi Arai
[SI-LIST] Re: ask for comments on high frequency filter design - Steve Rogers
[SI-LIST] How to add parellel terminator in IBIS - Pang Ning (Peter)
[SI-LIST] ACHIEVABLE TOLERANCE OF PCB TRACE WIDTH ? - Steve Rogers
[SI-LIST] Re: ask for comments on high frequency filter design - Chandrasekhar Arun
[SI-LIST] Re: Job Opportunity - Russel Hughes
[SI-LIST] Re: ask for comments on high frequency filter design - Swanson, Dan
[SI-LIST] Re: Coax vs. Microstrip - Swanson, Dan
[SI-LIST] Re: How to add parellel terminator in IBIS - Ingraham, Andrew
[SI-LIST] Re: Job Opportunity - Jon Powell
[SI-LIST] Re: Job Opportunity - Scott McMorrow
[SI-LIST] FW: How to add parellel terminator in IBIS - Jon Powell
[SI-LIST] Re: Job Opportunity - Russel Hughes
[SI-LIST] Re: How to add parellel terminator in IBIS - Dunbar, Tony
[SI-LIST] Re: Job Opportunity - Ken Cantrell
(no subject) - Suresh.K
[SI-LIST] Re: (no subject) - San Miguel, Shane
[SI-LIST] Re: Coax vs. Microstrip - e.sweetman
[SI-LIST] Re: FW: How to add parellel terminator in IBIS - Muranyi, Arpad
[SI-LIST] Re: (no subject) - Ron Miller
[SI-LIST] HPSICE error - Bob Patel
[SI-LIST] Temperature variable in SI simulation - Chetan Jadhav
[SI-LIST] Re: Temperature variable in SI simulation - Luca Giacotto
[SI-LIST] PC Parallel port to 3V3 - Ian Lewis
[SI-LIST] Re: PC Parallel port to 3V3 - Robert Plant
[SI-LIST] Ground clearance at connector vias - Fabrizio Zanella
[SI-LIST] laplace errors - Alicia Corrales Chanca
[SI-LIST] Re: Ground clearance at connector vias - Jim G Roberts
[SI-LIST] Re: Ground clearance at connector vias - Scott McMorrow
[SI-LIST] Re: PC Parallel port to 3V3 - Christopher . Crowley
[SI-LIST] Re: Ground clearance at connector vias - Ken Willis
[SI-LIST] Re: HPSICE error - Ingraham, Andrew
[SI-LIST] Re: Temperature variable in SI simulation - Ingraham, Andrew
[SI-LIST] Re: Ground clearance at connector vias - Christian Schuster
[SI-LIST] Re: laplace errors - Ingraham, Andrew
[SI-LIST] Re: Ground clearance at connector vias - Scott McMorrow
[SI-LIST] (No Subject) - GEORGE VARGHESE
[SI-LIST] Re: (No Subject) - San Miguel, Shane
[SI-LIST] Hspice vs Raphael - Sudha Thiru
[SI-LIST] Re: Temperature variable in SI simulation - Chetan Jadhav
[SI-LIST] Re: Ground clearance at connector vias - Jim G Roberts
[SI-LIST] Re: (No Subject) - Russel Hughes
[SI-LIST] Re: Ground clearance at connector vias - Scott McMorrow
[SI-LIST] Re: Ground clearance at connector vias - Jim G Roberts
[SI-LIST] Re: Ground clearance at connector vias - Scott McMorrow
[SI-LIST] stitched via shielding - Denomme, Paul S.
[SI-LIST] Re: stitched via shielding - ray_waugh
[SI-LIST] Re: Temperature variable in SI simulation - Muranyi, Arpad
[SI-LIST] Question about power delivery to silicon in a BGA package - Tegan Campbell
[SI-LIST] FW: Ground clearance at connector vias - Lawrence Williams
[SI-LIST] Re: Question about power delivery to silicon in a BGA package - Larry Barnes
[SI-LIST] EMI/EMC Engineer Job Opportunity - Westbrook, Scott
[SI-LIST] Re: Question about power delivery to silicon in a BGA package - Pat Diao
[SI-LIST] Re: laplace errors - Luca Giacotto
[SI-LIST] PECL design: trace impedance - Chetan Jadhav
[SI-LIST] Re: Question about power delivery to silicon in a BGA package - Chandrasekhar Arun
[SI-LIST] crosstalk-FastCap - manthos labropoulos
[SI-LIST] Re: Question about power delivery to silicon in a BGA package - Ingraham, Andrew
[SI-LIST] Re: : TDR extender cable, 1m, Tektronix PN 012-1220-00 for my 11801B scope. - Doug Hopperstad
[SI-LIST] Re: Question about power delivery to silicon in a BGA package - Chandrasekhar Arun
[SI-LIST] Re: : TDR extender cable, 1m, Tektronix PN 012-1220-00 for my 11801B scope. - Rich Peyton
[SI-LIST] Re: Question about power delivery to silicon in a BGA package - Larry Barnes
[SI-LIST] Re: Question about power delivery to silicon in a BGA package - Ingraham, Andrew
[SI-LIST] Re: : TDR extender cable, 1m, Tektronix PN 012-1220-00 for my 11801B scope. - Tom Dagostino
[SI-LIST] Need some Info on Inductance.. - Abhijit Mahajan
[SI-LIST] SPI 4-2 question(s) - Vadim Heyfitch
[SI-LIST] Re: Need some Info on Inductance.. - X2Y
[SI-LIST] Re: Need some Info on Inductance.. - Ray Anderson
[SI-LIST] Capacitor spice models which include dielectric losses - Harvey, Wilbur
[SI-LIST] Re: SPI 4-2 question(s) - Vinu Arumugham
[SI-LIST] Re: Capacitor spice models which include dielectric losses - Mike Khusid
[SI-LIST] PLL spectrum... - Tim Lu
[SI-LIST] Re: PLL spectrum... - Parthasarathy Sampath
[SI-LIST] Re: PLL spectrum...[follow up] - Parthasarathy Sampath
[SI-LIST] PCB manufactures control impedance report! - Avi Hayun
[SI-LIST] Star-rcxt: About parameter priority of mapping file - Bi Han
[SI-LIST] Skew and Jitter - SI Eng
[SI-LIST] HyperLynx Lunch and Learn - Z_Hashemi
[SI-LIST] RC termination - Nimish Aggarwal
[SI-LIST] Re: RC termination - Chetan Jadhav
[SI-LIST] a problem about PLL bypass - lu Haizhao
[SI-LIST] Re: a problem about PLL bypass - Yehuda Yizraeli
[SI-LIST] Re: a problem about PLL bypass - lu Haizhao
[SI-LIST] Re: a problem about PLL bypass - steve weir
[SI-LIST] Re: RC termination - Harjeet Singh Randhawa
[SI-LIST] Re: Capacitor spice models which include dielectric losses - Bart Bouma
[SI-LIST] SPI 2003 hotel reservation deadline - Carla Giachino
[SI-LIST] 1 analogic to 1 digital - Alicia Corrales Chanca
[SI-LIST] Re: Need some Info on Inductance.. - Rich Peyton
[SI-LIST] question regarding IBIS - ray_waugh
[SI-LIST] Re: question regarding IBIS - Jon Powell
[SI-LIST] Re: RC termination - Ingraham, Andrew
[SI-LIST] Re: Skew and Jitter - James_R_Jones
[SI-LIST] Re: Skew and Jitter - Todd Westerhoff
[SI-LIST] Re: Capacitor spice models which include dielectric losses - polus
[SI-LIST] Re: Skew and Jitter - SI Eng
[SI-LIST] Re: Skew and Jitter - Todd Westerhoff
[SI-LIST] What software to design multilayer PCB - zhou lin