FreeLists / si-list / [SI-LIST] Re: Hyperlynx modelling of 'wire over ground'

["Curt McNamara" <CurtM@xxxxxxxxxxx>]

So the wire is surrounded by:
Insulation (er =3D ?)=20
Then air (er =3D 1) (maybe we can neglect if wire is secured to board?)
then FR-4 (er =3D ~4)

This would be the stack-up for the rework wire, while the trace would be =
at "Layer 2" with just FR-4 underneath.

                                Curt


Curt McNamara, P.E.=A0// principal electrical engineer=20
Logic Product Development
411 Washington Ave. N. Suite 400
Minneapolis, MN 55401
T // 612.436.5178
F // 612.672.9489
www.logicpd.com=20
/ / / / / / / / / / / / / / / / / / / / / / / / /=20
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-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] =
On Behalf Of Jennings, Kevin F
Sent: Wednesday, February 20, 2008 3:00 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Hyperlynx modelling of 'wire over ground'

Curt,


Yes your description of the circuit is accurate and yes there is an =
actual wire added on the PCB which is why I picked the 'wire over =
ground' element to model this (prior to actually putting the wire on the =
board).



The relatively accurate prediction of signal quality when dealing with =
PCB traces but relatively poor prediction when adding another driver and =
a single physical wire to the model was rather surprising.


My question here was mainly to see whether or not anyone else had tried =
to model a rework wire (and/or multiple drivers) to a PCB and had =
HyperLynx accurately predict (or not) the resulting waveform.



I haven't totally ruled out user error on my part, and still need to go =
back and re-validate that my LineSim representation is an adequate =
representation of the PCB (apparently if I had LineSim EXT I could =
export the net from BoardSim and import it into LineSim...sigh).  From =
there maybe try to trace down what differences between model and reality =
that could explain the discrepancy, and if all that fails, open a case =
with the good folks at Mentor and see if they can explain the =
difference.



I definitely agree about the series termination, that's how I design =
things but when tasked with trying to salvage something one has to do =
what one has to do.



Thanks for your input (and to all the others who've responded here and =
privately).



Kevin Jennings

-----Original Message-----
From: Curt McNamara [mailto:CurtM@xxxxxxxxxxx]
Sent: Wednesday, February 20, 2008 10:10 AM
To: Jennings, Kevin F; si-list@xxxxxxxxxxxxx
Subject: RE: [SI-LIST] Hyperlynx modelling of 'wire over ground'



There are several possibilities. From your description it appears you =
have a net with driver and multiple receivers in LineSim. You then add =
another transmission line with another driver and tie it into the first =
transmission line. Is that correct? Do you have both drivers active at =
the same time?



In the real board, is this second transmission line an actual wire on a =
PCB?



If these are all correct, here are some possibilities:

The actual wire does not have the impedance you model.

The actual wire has significant parasitics which you haven't modeled.



In general we avoid multiple drivers on a single line. There are several =
issues: output circuitry may not parallel nicely; propagation delay to =
inputs may be different; pulses originating at different line lengths =
arrive at receivers at different times, leading to reflections like you =
observe.



For the case you described we would commonly use series termination at =
the driver. Small resistors can often be placed between package leads =
and solder pads to prove this out.



                                                Curt





Curt McNamara, P.E. // principal electrical engineer

Logic Product Development

411 Washington Ave. N. Suite 400

Minneapolis, MN 55401

T // 612.436.5178

F // 612.672.9489

www.logicpd.com

/ / / / / / / / / / / / / / / / / / / / / / / / /

This message (including any attachments) contains confidential =
information intended for a specific individual and purpose, and is =
protected by law. If you are not the intended recipient, you should =
delete this message and are hereby notified that any disclosure, =
copying, or distribution of this message, or the taking of any action =
based on it, is strictly prohibited.







-----Original Message-----

From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] =
On Behalf Of Jennings, Kevin F

Sent: Tuesday, February 19, 2008 7:59 AM

To: si-list@xxxxxxxxxxxxx

Subject: [SI-LIST] Hyperlynx modelling of 'wire over ground'



I'm consulting on a signal integrity issue on a board and trying to use =
Hyp=3D

erLynx to model proposed changes to the net.  The BoardSim model of the =
PCB=3D

 net appears to be a fairly accurate model of reality.  When I construct =
a =3D

LineSim model of the net it also seems to be a fairly accurate model of =
rea=3D

lity.  However, when I then add a 'wire over ground' to the Linesim =
model t=3D

he HyperLynx predicted waveforms seem to be nowhere near what is =
actually s=3D

een on the reworked PCBA.



The net in question is ~20 inches long, ~40MHz clock driven by a single =
dri=3D

ver into ~50 ohm PCB with 7 loads distributed along the line; the single =
dr=3D

iver does not have nearly enough oomph to produce a clean edge on the =
incid=3D

ent wave.  What I was proposing as a rework was a wire from a second =
driver=3D

 into an appropriate spot in the net.  The Linesim model shows a =
relatively=3D

 clean edge now but adding the wire on the PCBA does not.  Instead there =
is=3D

 a ~1V 5 ns wide dip in the signal after the first incident wave switch =
tha=3D

t in some of the loads is dipping back near the Vih spec limit.



Varying the Linesim 'wire over ground' parameters (wire radius and =
distance=3D

 from ground) suggests that the proposed rework is relatively =
insensitive t=3D

o both which then suggests that the major contributor to the change in =
the =3D

signal (from the model's perspective) is the change in the net topology =
and=3D

 available drive that occurs by adding the second driver and wire, which =
is=3D

 as I expected.



The fact that reality diverges so far from the model basically renders =
the =3D

model useless for testing changes from a model perspective.



Does Linesim maybe not do well when modeling multiple drivers on a net?

Does Linesim maybe not model 'wire over ground' very well?



Anything else that I'm missing that might explain the wide discrepancy =
betw=3D

een model and reality when wiring in a second driver given that the =
model w=3D

as fairly accurate with the unmodified PCBA?



Thanks for your input.



Kevin Jennings



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