FreeLists / si-list / [SI-LIST] Re: Hyperlynx modelling of 'wire over ground'

["Peterson, James F (EHCOE)" <james.f.peterson@xxxxxxxxxxxxx>]

Regarding your comment :
"the single driver does not have nearly enough oomph to produce a clean
edge on the incident wave."

Show me a buffer that can drive a clock line cleanly to 7 loads, I'd
like to buy that...I believe this is a major flaw in their design (they
should have hired you before they got so far down the road).

Regards,
Jim Peterson
Honeywell

-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Curt McNamara
Sent: Wednesday, February 20, 2008 10:10 AM
To: Jennings, Kevin F; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Hyperlynx modelling of 'wire over ground'

There are several possibilities. From your description it appears you =
=3D
have a net with driver and multiple receivers in LineSim. You then add =
=3D
another transmission line with another driver and tie it into the first
=3D
transmission line. Is that correct? Do you have both drivers active at =
=3D
the same time?

In the real board, is this second transmission line an actual wire on a
=3D
PCB?=3D20

If these are all correct, here are some possibilities:
The actual wire does not have the impedance you model.
The actual wire has significant parasitics which you haven't modeled.

In general we avoid multiple drivers on a single line. There are several
=3D
issues: output circuitry may not parallel nicely; propagation delay to =
=3D
inputs may be different; pulses originating at different line lengths =
=3D
arrive at receivers at different times, leading to reflections like you
=3D
observe.

For the case you described we would commonly use series termination at =
=3D
the driver. Small resistors can often be placed between package leads =
=3D
and solder pads to prove this out.

                                                Curt


Curt McNamara, P.E.=3DA0// principal electrical engineer=3D20
Logic Product Development
411 Washington Ave. N. Suite 400
Minneapolis, MN 55401
T // 612.436.5178
F // 612.672.9489
www.logicpd.com=3D20
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This message (including any attachments) contains confidential =3D
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based on it, is strictly prohibited.



-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
=3D
On Behalf Of Jennings, Kevin F
Sent: Tuesday, February 19, 2008 7:59 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Hyperlynx modelling of 'wire over ground'

I'm consulting on a signal integrity issue on a board and trying to use
=3D
Hyp=3D3D
erLynx to model proposed changes to the net.  The BoardSim model of the
=3D
PCB=3D3D
 net appears to be a fairly accurate model of reality.  When I construct
=3D
a =3D3D
LineSim model of the net it also seems to be a fairly accurate model of
=3D
rea=3D3D
lity.  However, when I then add a 'wire over ground' to the Linesim =3D
model t=3D3D
he HyperLynx predicted waveforms seem to be nowhere near what is =3D
actually s=3D3D
een on the reworked PCBA.

The net in question is ~20 inches long, ~40MHz clock driven by a single
=3D
dri=3D3D
ver into ~50 ohm PCB with 7 loads distributed along the line; the single
=3D
dr=3D3D
iver does not have nearly enough oomph to produce a clean edge on the =
=3D
incid=3D3D
ent wave.  What I was proposing as a rework was a wire from a second =3D
driver=3D3D
 into an appropriate spot in the net.  The Linesim model shows a =3D
relatively=3D3D
 clean edge now but adding the wire on the PCBA does not.  Instead there
=3D
is=3D3D
 a ~1V 5 ns wide dip in the signal after the first incident wave switch
=3D
tha=3D3D
t in some of the loads is dipping back near the Vih spec limit.

Varying the Linesim 'wire over ground' parameters (wire radius and =3D
distance=3D3D
 from ground) suggests that the proposed rework is relatively =3D
insensitive t=3D3D
o both which then suggests that the major contributor to the change in =
=3D
the =3D3D
signal (from the model's perspective) is the change in the net topology
=3D
and=3D3D
 available drive that occurs by adding the second driver and wire, which
=3D
is=3D3D
 as I expected.

The fact that reality diverges so far from the model basically renders =
=3D
the =3D3D
model useless for testing changes from a model perspective.

Does Linesim maybe not do well when modeling multiple drivers on a net?
Does Linesim maybe not model 'wire over ground' very well?

Anything else that I'm missing that might explain the wide discrepancy =
=3D
betw=3D3D
een model and reality when wiring in a second driver given that the =3D
model w=3D3D
as fairly accurate with the unmodified PCBA?

Thanks for your input.

Kevin Jennings

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