FreeLists / si-list / [SI-LIST] Random behaiour of Virtex 4 FPGA

["vijayan" <s.vijayan@xxxxxxxxxxxxx>]

Hi all,
I am using  Virtex 4 FPGA (XC4VFX100) in our application. In this, we find some 
random behaiour of FPGA.

Whenever the bit file is loaded into the FPGA, there is a drop in core 
voltage(power module getting shutdown).Bit file gives such random behaviour 
uses particular three banks for its logic. Here we thought like this, it may be 
due to any internal damage in FPGA IOBs around that three banks.

Here is the few points added,

* We tried with a bit file that has high logic utilization (logic is not on 
that faulty banks. it uses other banks). It works fine.
* Also we tried some other bit files with low logic utilization using that 
banks is working properly (power won't disturbed).
* Whatever signals from that faulty banks are not shorted with VCC/GND. We 
probed it.
* Good core voltage power solution.

Pls suggest me the solution to identify the exact source of that random 
behaviour.

Regards,
Vijayan Sivamani
------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field

or to administer your membership from a web page, go to:
http://www.freelists.org/webpage/si-list

For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field


List technical documents are available at:
                http://www.si-list.net

List archives are viewable at:     
                http://www.freelists.org/archives/si-list
or at our remote archives:
                http://groups.yahoo.com/group/si-list/messages
Old (prior to June 6, 2001) list archives are viewable at:
                http://www.qsl.net/wb6tpu