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[SI-LIST] Re: PCI Rise/Fall Time

From: Kenny Frohlich <kenny_frohlich@xxxxxxxxx>
To: Jon Keeble <jkeeble@xxxxxxxxxxxx>, si-list@xxxxxxxxxxxxx
Date: Sat, 17 Feb 2007 23:33:07 -0800 (PST)
Jon,
  I'm sorry I was not clear.  PCI bus is connected in a daisy-chain topology, 
but the PCI clocks are point-to-point (each device has its own clock and they 
come from the same clock buffer).
   
  Thanks,
  Kenny
  
Jon Keeble <jkeeble@xxxxxxxxxxxx> wrote:
  Hi Kenny

A series sourced daisy chain is just asking for trouble.

The kind of trouble you won't see with a 100MHz scope.

Daisy chain is not good for PCI clocks, but you might improve things by
either
- replace the series source resistor with 0R
- far-end parallel terminate; the hi and lo levels will move to towards the
centre, but you will reduce the 'ledging' that is sure to be present.

Without a model it is trial and error, but doable.

Moral; don't daisy chain clocks.

Good Luck

Jon Keeble
**********************
JK Consulting Pty Ltd


----- Original Message ----- 
From: "Kenny Frohlich" 
To: ; ;

Sent: Friday, February 16, 2007 5:03 PM
Subject: [SI-LIST] Re: PCI Rise/Fall Time


>
> Aubrey,
> The clocks are monotonic and in spec. The measured slew rates are about
0.8 V/ns which is slow compared to spec (1 - 4 V/ns).
> Yes, slew rate is the only spec I'm failing. Both my setup and hold
times are good (within spec).
> May be I should not try to meet the slew rates in the spec since the PCI
standard specifies a test load for measuring the slew rates and my PCI bus
is a daisy-chain topology which is not the same test condition.
>
> Thanks,
> Kenny
>
> Aubrey_Sparkman@xxxxxxxx wrote:
> Kenny,
> Are the clocks monotonic and in spec? How much less than 1 are your
> slew rates? =20
>
> Jim is probably right.
>
> Slower (closer to 4) slew rates are easier to get ringing under control,
> but Faster slew rates (closer to 1) are better from a jitter perspective
> - not very relevant for PCI-33.
> IF slew rate is the only spec that are you failing and none of your
> devices are slots, the question I would ask is: Can anyone give me a
> reason to even try to slow down the slow rate and fix?
>
>
> Aubrey Sparkman=20
> Enterprise Engineering Signal Integrity Team
> Dell, Inc.=20
> Aubrey_Sparkman@xxxxxxxx=20
> (512) 723-3592
>
> The Greatest Pleasure in Life is Doing what People say can't be done...
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
> On Behalf Of Peterson, James F (EHCOE)
> Sent: Thursday, February 15, 2007 5:59 AM
> To: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: PCI Rise/Fall Time
>
> Kenny,
>
> The PCI standard specifies a test load for measuring the slew rates. It
> does not include the 33 ohm series resistor, so you'll be ok. (I think
> it's still 1k Pullup, 1K Pulldown, and a 10pf pulldown....)
>
> Jim Peterson
> Honeywell
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
> On Behalf Of Kenny Frohlich
> Sent: Thursday, February 15, 2007 12:29 AM
> To: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] PCI Rise/Fall Time
>
> Hi All,
> I have a design that has a 33MHz PCI bus. There are one master (CPU)
> and five PCI devices on the bus and these devices are connected in a
> daisy-chain topology. There's a serial termination of 33 Ohms at the
> beginning of the bus and an end termination of 3K at the end of the bus.
> The setup and hold times of this PCI bus in my design are within the
> spec.; however, the rise and fall times (slew rates) are not. The rates
> are too slow (less than 1) compared to the spec (1 to 4). Changing the
> value of the serial termination to O Ohm helps a little, but it still
> does not meet the spec. =3D20
> =3D20
> Can you help me fix this issue?
> =3D20
> Thanks,
> Kenny
> =3D20
> =3D20
> ---------------------------------
>



 
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[SI-LIST] Re: PCI Rise/Fall Time
From: Jon Keeble
[SI-LIST] Re: PCI Rise/Fall Time

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