Date Index for si-list, 02-2006

[si-list] || [02-2006 Date Index] [02-2006 Thread Index]

[SI-LIST] Differential impedance signals????? - kishore bachu
[SI-LIST] .tr0 file viewer - Naren Thesia
[SI-LIST] Re: .tr0 file viewer - Bi Han
[SI-LIST] Re: .tr0 file viewer - Andrew Burnside
[SI-LIST] European IBIS Summit at DATe 2006 - Third Call for Paper/Call for Participation - Ralf Bruening
[SI-LIST] Re: .tr0 file viewer - Ke Wang
[SI-LIST] Reflected Wave Switching - Silly Question. - Kedar P Apte
[SI-LIST] simulating mobile phone effects on circuits - Doug Smith
[SI-LIST] PHY PCS - Ravindra Johari
[SI-LIST] Re: PHY PCS - Edi Fraiman
[SI-LIST] Re: PHY PCS - Kedar P Apte
[SI-LIST] Re: PHY PCS - steve weir
[SI-LIST] Re: PHY PCS - Edi Fraiman
[SI-LIST] Re: Reflected Wave Switching - Silly Question. - Andrew Ingraham
[SI-LIST] edge coupled coated microstrip differential impedance - jerry_hu
[SI-LIST] Re: edge coupled coated microstrip differential impedance - Ing. Giancarlo Guida
[SI-LIST] Re: Reflected Wave Switching - Silly Question. - Lynne D. Green
[SI-LIST] Re: edge coupled coated microstrip differential impedance - Grasso, Charles
[SI-LIST] Session of interest to SI engineers at DesignCon 2006 - Pratt, Gary
[SI-LIST] Re: edge coupled coated microstrip differential impedance - Doug Brooks
[SI-LIST] help me - jagaveer25
[SI-LIST] Re: help me - steve weir
[SI-LIST] Re: help me - zhangkun 29902
[SI-LIST] Re: help me - Stefan Ludwig
[SI-LIST] Re: help me - Mahabala Shetty
[SI-LIST] Re: help me - zhangkun 29902
[SI-LIST] Re: help me - Andrew Ingraham
[SI-LIST] Re: edge coupled coated microstrip differentialimpedance - Lee Ritchey
[SI-LIST] Devlopment Eng. R.F. Filter Connectors - bruce harvie
[SI-LIST] Re: help me - steve weir
[SI-LIST] File Extension .fig - Jim Antonellis
[SI-LIST] Re: File Extension .fig - Ray Anderson
[SI-LIST] Re: help me - zhangkun 29902
[SI-LIST] Re: help me - steve weir
[SI-LIST] Re: help me - Andrew Ingraham
[SI-LIST] Good book - prasadsa
[SI-LIST] Re: edge coupled coated microstrip differential impedance - Loyer, Jeff
[SI-LIST] Analog/mixed signal Contract Engineer position - Priest, Edward
[SI-LIST] Re: Good book - Akhilesh CHANDRA
[SI-LIST] Re: Good book - Doug Martens
[SI-LIST] Re: edge coupled coated microstrip differential impedance - Andrew Ingraham
[SI-LIST] Ground/Power electrical modeling battery powered devices - Eoin Mc Gibney
[SI-LIST] Re: Help me - sunil.mekad
[SI-LIST] Re: Help me - stubenner
[SI-LIST] Re: Help me - Andrew Burnside
[SI-LIST] Re: Good book - Qazi Arif Iqbal
[SI-LIST] unsubscribe - Rane Hana
[SI-LIST] unsubscribe - Somesh Dhavala
[SI-LIST] Immunity to nearby wireless devices and EE undergrad programs - Doug Smith
[SI-LIST] Ethernet Multiplexers/Switches - Kedar P Apte
[SI-LIST] Re: PHY PCS - Ravindra Johari
[SI-LIST] Re: Help me - Andrew Burnside
[SI-LIST] Re: PHY PCS - Edi Fraiman
[SI-LIST] HSPICE - adding jitter to ethernet serial link - Ali Burney
[SI-LIST] Re: HSPICE - adding jitter to ethernet serial link - Ed Sayre III
[SI-LIST] 3D tool: CST / HFSS - ma mu
[SI-LIST] Skewed Silicon Parameters - james_r_jones
[SI-LIST] Re: Skewed Silicon Parameters - Steve Horne
[SI-LIST] Re: PHY PCS - Andrew Ingraham
[SI-LIST] Reflections - Babid A
[SI-LIST] Re: Reflections - Mike Greim
[SI-LIST] Re: Reflections - Andrew Ingraham
[SI-LIST] Re: Reflections - Qazi Arif Iqbal
[SI-LIST] Re: Skewed Silicon Parameters - Lynne D. Green
[SI-LIST] Interesting announcement regarding IBIS 4.1 - Pratt, Gary
[SI-LIST] Re: 3D tool: CST / HFSS - LI QIANG-R58304
[SI-LIST] Re: 3D tool: CST / HFSS - Jory McKinley
[SI-LIST] UnSubscribe - Vijay S CHACHRA
[SI-LIST] Re: 3D tool: CST / HFSS - Eoin Mc Gibney
[SI-LIST] AC termination - #CHUANG KENG HUA#
[SI-LIST] Signal Integrity Engineering position at Intel Corporation - Grossman, Brett
[SI-LIST] Xilinx simulation model validation - Buchs, Kevin J.
[SI-LIST] Re: Xilinx simulation model validation - Kai Keskinen
[SI-LIST] currnet through wire bond - Kamran Azizi
[SI-LIST] Microprocessor Platform Impedance. Characterization using VTT Tools - Heinrich.Smith
[SI-LIST] Re: AC termination - David Instone
[SI-LIST] [OFF-TOPIC] Signal Integrity Simplified book - Rui Pimenta
[SI-LIST] Re: [OFF-TOPIC] Signal Integrity Simplified book - Clewell, Craig
[SI-LIST] Re: [OFF-TOPIC] Signal Integrity Simplified book - Zabinski, Patrick J.
[SI-LIST] Re: currnet through wire bond - Christopher.Jakubiec
[SI-LIST] Capacitor Arrays for clock AC coupling - David Greig
[SI-LIST] Re: [OFF-TOPIC] Signal Integrity Simplified book - Julian Ferry
[SI-LIST] Re: Capacitor Arrays for clock AC coupling - steve weir
[SI-LIST] Re: Capacitor Arrays for clock AC coupling - Mikhail Matusov
[SI-LIST] Re: Capacitor Arrays for clock AC coupling - Jon Keeble
[SI-LIST] Re: [OFF-TOPIC] Signal Integrity Simplified book - steve weir
[SI-LIST] Re: Capacitor Arrays for clock AC coupling - steve weir
[SI-LIST] Fwd: EMCS-SCV Chapter Meeting, Tuesday February 14, 2006 - Ahmad Fallah
[SI-LIST] Differential Impedance of PCB Vias - Hirshtal Itzhak
[SI-LIST] Re: Differential Impedance of PCB Vias - Ing. Giancarlo Guida
[SI-LIST] Re: [OFF-TOPIC] Signal Integrity Simplified book - Fasig, Jonathan L.
[SI-LIST] Re: [OFF-TOPIC] Signal Integrity Simplified book - Lee Ritchey
[SI-LIST] Re: [OFF-TOPIC] Signal Integrity Simplified book - Buchs, Kevin J.
[SI-LIST] Re: [OFF-TOPIC] Signal Integrity Simplified book - Ken Cantrell
[SI-LIST] Re: [OFF-TOPIC] Signal Integrity Simplified book - steve weir
[SI-LIST] Re: Good book - Coe, Stephen
[SI-LIST] Re: [OFF-TOPIC] Signal Integrity Simplified book - Curt McNamara
[SI-LIST] Re: [OFF-TOPIC] Signal Integrity Simplified book - Ingo Kupper
[SI-LIST] Signal Integrity Simplified book - Eric Bogatin
[SI-LIST] Analog, "low-noise", "high frequency", board-level designer needed! - Kevin Pierpoint
[SI-LIST] Re: Good book - prasadsa
[SI-LIST] Re: Analog, "low-noise", "high frequency", board-level designerneeded! - Ken Cantrell
[SI-LIST] Package SI vs PCB SI - Scott McMorrow
[SI-LIST] Re: Package SI vs PCB SI - Hassan O. Ali
[SI-LIST] Re: Package SI vs PCB SI - Ing. Giancarlo Guida
[SI-LIST] Re: Package SI vs. PCB SI - Haller, Robert
[SI-LIST] Re: Package SI vs. PCB SI...thanks to Maxwell - Ing. Giancarlo Guida
[SI-LIST] Re: Package SI vs PCB SI - Jory McKinley
[SI-LIST] QLOGIC Ref. Designs - Kamran Azizi
[SI-LIST] Re: 3D tool: CST / HFSS - dgun
[SI-LIST] Re: currnet through wire bond - dgun
[SI-LIST] Re: currnet through wire bond - sunil bharadwaz
[SI-LIST] Re: HSPICE - adding jitter to ethernet serial link - Pratt, Gary
[SI-LIST] Re: HSPICE - adding jitter to ethernet serial link - Scott McMorrow
[SI-LIST] Re: Differential Impedance of PCB Vias - Hirshtal Itzhak
[SI-LIST] Re: Differential Impedance of PCB Vias - Ing. Giancarlo Guida
[SI-LIST] Re: HSPICE - adding jitter to ethernet serial link - Chris Cheng
[SI-LIST] Ethernet standards coding and data frequency - Jean_Pierre . Bouthemy
[SI-LIST] Re: Differential Impedance of PCB Vias - Yuming Tao
[SI-LIST] Re: HSPICE - adding jitter to ethernet serial link - Hassan O. Ali
[SI-LIST] Re: HSPICE - adding jitter to ethernet serial link - Chris Cheng
[SI-LIST] Re: HSPICE - adding jitter to ethernet serial link - Alfred P. Neves
[SI-LIST] Re: HSPICE - adding jitter to ethernet serial link - Beal, Weston
[SI-LIST] Re: HSPICE - adding jitter to ethernet serial link - Ed Sayre III
[SI-LIST] Re: HSPICE - adding jitter to ethernet serial link - Hassan O. Ali
[SI-LIST] Re: HSPICE - adding jitter to ethernet serial link - Hassan O. Ali
[SI-LIST] Re: HSPICE - adding jitter to ethernet serial link - Chris Cheng
[SI-LIST] Re: currnet through wire bond - Javier DeLaCruz
[SI-LIST] Re: HSPICE - adding jitter to ethernet serial link - Hassan O. Ali
[SI-LIST] Re: HSPICE - adding jitter to ethernet serial link - steve weir
[SI-LIST] Re: Differential Impedance of PCB Vias - Kai Keskinen
[SI-LIST] Re: HSPICE - adding jitter to ethernet serial link - Chris Cheng
[SI-LIST] Re: HSPICE - adding jitter to ethernet serial link - Alfred P. Neves
[SI-LIST] Re: HSPICE - adding jitter to ethernet serial link - Chris Cheng
[SI-LIST] Re: HSPICE - adding jitter to ethernet serial link - Hassan O. Ali
[SI-LIST] Re: HSPICE - adding jitter to ethernet serial link - steve weir
[SI-LIST] controlling test variables during troubleshooting - Doug Smith
[SI-LIST] Re: HSPICE - adding jitter to ethernet serial link - Hassan O. Ali
[SI-LIST] Re: AC termination - #CHUANG KENG HUA#
[SI-LIST] Re: DesignCon 2006 material on power distribution network design methodologies posted - Istvan Novak - Board Design Technology
[SI-LIST] Re: HSPICE - adding jitter to ethernet serial link - Scott McMorrow
[SI-LIST] Re: HSPICE - adding jitter to ethernet serial link - steve weir
[SI-LIST] Re: HSPICE - adding jitter to ethernet serial link - Vinu Arumugham
[SI-LIST] Re: DesignCon 2006 material on power distribution network design methodologies posted - Peterson, James F (FL51)
[SI-LIST] Effect of Pwr-Gnd plane pairing vs. non-paired planes on signal return currents - Alex Horvath
[SI-LIST] Re: Effect of Pwr-Gnd plane pairing vs. non-paired planes on signal return currents - Aubrey_Sparkman
[SI-LIST] Re: HSPICE - adding jitter to ethernet serial link - Hassan O. Ali
[SI-LIST] Re: Effect of Pwr-Gnd plane pairing vs. non-paired planes on signal return currents - Vinu Arumugham
[SI-LIST] Re: Effect of Pwr-Gnd plane pairing vs. non-paired planes on signal return currents - Aubrey_Sparkman
[SI-LIST] Re: Effect of Pwr-Gnd plane pairing vs. non-paired planes on signal return currents - Yuming Tao
[SI-LIST] Re: Effect of Pwr-Gnd plane pairing vs. non-paired planes on signal return currents - George Peterson
[SI-LIST] Re: Effect of Pwr-Gnd plane pairing vs. non-paired planes on signal return currents - Aubrey_Sparkman
[SI-LIST] Re: Effect of Pwr-Gnd plane pairing vs. non-paired planes on signal return currents - steve weir
[SI-LIST] Re: Effect of Pwr-Gnd plane pairing vs. non-paired planes on signal return currents - Alex Horvath
[SI-LIST] Re: HSPICE - adding jitter to ethernet serial link - Hassan O. Ali
[SI-LIST] Re: HSPICE - adding jitter to ethernet serial link - steve weir
[SI-LIST] Re: HSPICE - adding jitter to ethernet serial link - Hassan O. Ali
[SI-LIST] FW: Re: currnet through wire bond - jeff.latourrette
[SI-LIST] Re: Effect of Pwr-Gnd plane pairing vs. non-paired planes on signal return currents - Perry Qu
[SI-LIST] Re: Effect of Pwr-Gnd plane pairing vs. non-paired planes on signal return currents - George Peterson
[SI-LIST] Re: DesignCon 2006 material on power distribution network design methodologies posted - Larry Smith
[SI-LIST] SI Employment Opportunity at Altera: Posting - Larry Smith
[SI-LIST] Looking for mini x12 board to cable system....... - Mike Greim
[SI-LIST] Electrical wiring questions - Mike S.
[SI-LIST] Re: Electrical wiring questions - steve weir
[SI-LIST] Re: currnet through wire bond: correction - dgun
[SI-LIST] Re: Electrical wiring questions - dgun
[SI-LIST] Re: Electrical wiring questions - Mike S.
[SI-LIST] Re: Electrical wiring questions - Curt McNamara
[SI-LIST] Re: Electrical wiring questions - Curt McNamara
[SI-LIST] Re: Digest Number 1730 - Faraydon Pakbaz
[SI-LIST] Re: Digest Number 1730 - steve weir
[SI-LIST] S-parameter to Circuit Model extraction? - 델타소년
[SI-LIST] Re: S-parameter to Circuit Model extraction? - Ing. Giancarlo Guida
[SI-LIST] Re: S-parameter to Circuit Model extraction? - Eoin Mc Gibney
[SI-LIST] Re: S-parameter to Circuit Model extraction? - Faraydon Pakbaz
[SI-LIST] help request: 3D model library - Ing. Giancarlo Guida
[SI-LIST] Re: attached files (was Re: Digest Number 1730) - Andrew Ingraham
[SI-LIST] Re: S-parameter to Circuit Model extraction? - ChangMyung RYU
[SI-LIST] Re: S-parameter to Circuit Model extraction? - Dmitriev-Zdorov, Vladimir
[SI-LIST] Re: S-parameter to Circuit Model extraction? - Faraydon Pakbaz
[SI-LIST] Re: Electrical wiring questions - Mike S.
[SI-LIST] Re: Electrical wiring questions - steve weir
[SI-LIST] SATA II Electrical Specification - Cortex.Chen
[SI-LIST] Can we drive 100Mhz SSTL_18 with standard ALVC or other 1.8V logic - Jai Shanker
[SI-LIST] Re: Can we drive 100Mhz SSTL_18 with standard ALVC or other 1.8V logic - steve weir
[SI-LIST] Re: Can we drive 100Mhz SSTL_18 with standard ALVC or other 1.8V logic - Faraydon Pakbaz
[SI-LIST] optimization of curve-fit data - Zabinski, Patrick J.
[SI-LIST] Re: Electrical wiring questions - Curt McNamara
[SI-LIST] Optimization by HSPICE of curve-fit data - Dr. Edward P. Sayre
[SI-LIST] DDR2 design - Ivor Bowden
[SI-LIST] Re: DDR2 design - Abe Riazi
[SI-LIST] Re: DDR2 design - steve weir
[SI-LIST] Re: DDR2 design - Ivor Bowden
[SI-LIST] Re: DDR2 design - Scott McMorrow
[SI-LIST] Re: DDR2 design - Chris Cheng
[SI-LIST] Re: DDR2 design - Chris Cheng
[SI-LIST] Re: DDR2 design - steve weir
[SI-LIST] Re: DDR2 design - steve weir
[SI-LIST] Re: DDR2 design - steve weir
[SI-LIST] Re: Can we drive 100Mhz SSTL_18 with standard ALVC or other 1.8V logic - Jai Shanker
[SI-LIST] Re: DDR2 design - Jai Shanker
[SI-LIST] Ground Pour in Signal Layers - Pradeep RSA
[SI-LIST] Re: Ground Pour in Signal Layers - steve weir
[SI-LIST] Re: DDR2 design - Peterson, James F (FL51)
[SI-LIST] Re: DDR2 design - Zhou, Xingling (Mick)
[SI-LIST] Re: Ground Pour in Signal Layers - Yuming Tao
[SI-LIST] Re: Ground Pour in Signal Layers - Richard P EVANS
[SI-LIST] Re: DDR2 design - Ivor Bowden
[SI-LIST] Re: Ground Pour in Signal Layers - Ivor Bowden
[SI-LIST] Re: Ground Pour in Signal Layers - steve weir
[SI-LIST] Re: Ground Pour in Signal Layers - Chris Padilla (cpad)
[SI-LIST] Re: Ground Pour in Signal Layers - Lee Ritchey
[SI-LIST] Re: Ground Pour in Signal Layers - Haller, Robert
[SI-LIST] Re: DDR2 design - Grasso, Charles
[SI-LIST] Re: Ground Pour in Signal Layers - Lee Ritchey
[SI-LIST] ICM 1.1 approved as an ANSI standard! - Mirmak, Michael
[SI-LIST] Looking for 3D fullwave EM modeling tools - Mohammad Ali
[SI-LIST] Re: Looking for 3D fullwave EM modeling tools - steve weir
[SI-LIST] Re: Optimization by HSPICE of curve-fit data - Joel
[SI-LIST] Re: Looking for 3D fullwave EM modeling tools - Grasso, Charles
[SI-LIST] Why do we use transformer for DC blocking in ethernet connection ? - glenchen
[SI-LIST] Re: Why do we use transformer for DC blocking in ethernet connection ? - steve weir
[SI-LIST] What is correctly placement of Transformer? Locate Near IC or RJ45 CONN? Why? - ªü¥È
[SI-LIST] cable discharge, devices, and standards - Doug Smith
[SI-LIST] Re: What is correctly placement of Transformer? Locate Near IC or RJ45 CONN? Why? - steve weir
[SI-LIST] Macromodeling software available from Politecnico di Torino - sivi.cla@xxxxxxxxx
[SI-LIST] Re: What is correctly placement of Transformer? Locate Near IC or RJ45 CONN? Why? - Curt McNamara
[SI-LIST] Re: Type of Driver - Dr. Edward P. Sayre
[SI-LIST] Re: Macromodeling software available from Politecnico di Torino - Faraydon Pakbaz
[SI-LIST] Integrated vs. discrete magnetics for Ethernet - Chauhan, Prakash
[SI-LIST] European IBIS Summit at DATe 2006 - Final Call for Paper/Call for Participation - Ralf Bruening
[SI-LIST] Re: Integrated vs. discrete magnetics for Ethernet - Chris Padilla (cpad)
[SI-LIST] Re: Integrated vs. discrete magnetics for Ethernet - Chauhan, Prakash
[SI-LIST] Re: Macromodeling software available from Politecnico di Torino - Albert Ruehli
[SI-LIST] Re: Ground Pour in Signal Layers - Haller, Robert
[SI-LIST] Re: Ground Pour in Signal Layers - Lee Ritchey
[SI-LIST] Re: Why do we use transformer for DC blocking in ethernet connection ? - Tang, George
[SI-LIST] Re: Why do we use transformer for DC blocking in ethernet connection ? - Tom Biggs
[SI-LIST] How to convert Hspice model - Joel Brown
[SI-LIST] Re: Ground Pour in Signal Layers - Gerry Gagnon
[SI-LIST] Re: How to convert Hspice model - Hargin, Bill
[SI-LIST] Re: Integrated vs. discrete magnetics for Ethernet - Jai Shanker
[SI-LIST] Re: DDR2 design - Dhiraj Kiran
[SI-LIST] FW: RE: DDR2 design - Dhiraj Kiran
[SI-LIST] Re: SATA II Electrical Specification - Charles Hill
[SI-LIST] Re: Integrated vs. discrete magnetics for Ethernet - Grasso, Charles
[SI-LIST] Re: Ground Pour in Signal Layers - Lee Ritchey
[SI-LIST] Re: Ground Pour in Signal Layers - Grasso, Charles
[SI-LIST] Re: Ground Pour in Signal Layers - Lee Ritchey
[SI-LIST] Re: Integrated vs. discrete magnetics for Ethernet - Chris Padilla (cpad)
[SI-LIST] Re: Ground Pour in Signal Layers - Robert Sefton
[SI-LIST] Re: Ground Pour in Signal Layers - Curt McNamara
[SI-LIST] Re: Integrated vs. discrete magnetics for Ethernet - Curt McNamara
[SI-LIST] Re: Ground Pour in Signal Layers - Gary Schneider
[SI-LIST] Re: How to convert Hspice model - Kai Keskinen
[SI-LIST] Re: How to convert Hspice model - Mohammad Ali
[SI-LIST] Re: Ground Pour in Signal Layers - Gerry Gagnon