FreeLists / si-list / [SI-LIST] Re: Fan-out in TTL and CMOS

[Hal Murray <hmurray@xxxxxxxxxxxxxxx>]

> TTL is dead as a technology, so worrying about fanout is behind us.
> By the way, ECL is dead as well.

LS, S, and F families had similar loading rules.  They seem pretty dead too.

I generally use HC for odds&ends discrete logic (aka jelly beans) these days. 
 (There are several other xxC families that are faster.)

Is there a modern replacement for the 7406?  (OC inverter good for 30V)  What 
other real-old chips don't have a modern replacement?

The equivalent of the old loading rules are still important if you are using 
CMOS gates to drive non-CMOS inputs, say to drive a LED or a transistor.


Does the ECL that is dead include PECL and LVPECL?  If they aren't dead yet, 
what is their projected lifetime?

What is filling the ecological niche that ECL used to own?  LVDS?  ...

Not all that many years ago, differential ECL was the high end for clock 
distribution in large systems.  What do people use today?  Anybody still 
designing busses on backplanes that need large-fanout low-skew clock 
distributions?  I'd guess most of the designs are using point to point busses 
with clock forwarding and/or high speed serial links.


There are/were a lot of neat chips available in ECL/PECL.  OnSemi's ECLinPS 
line have serious SI advantages if you don't need density.  Many are 
available in 3.3V for LVPECL.

I've always wanted to build something that could use the MC100E195 - 
programmable delay with 80 pS steps.  xx196 has 10 pS steps.

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