FreeLists / si-list / [SI-LIST] Re: DDR-1 termination (short point-to-point)

["Julia Nekrylova" <JNEKRYLO@xxxxxxxxxx>]

A simple SI and timing simulation would not include SSN effects (ground
bounce, power noise) that in the presence of terminations are far more
manageable. This is just a reminder that SSN can kill DDR performance,
not just reflections and crosstalk.

Regards,
Julia

-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of De Paepe, Kristiaan
Sent: Friday, February 04, 2005 7:15 AM
To: 'af@xxxxxx'; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: DDR-1 termination (short point-to-point)

Anders,
Is this DDR333?
In my experience this requires SSTL2C2 on the V2P for the datalines,
strobes
& clocks; these pins are quite fast (0.7 ns ?), putting you right on the
edge with 5cm. The low impedance of the DDR drivers will probably kill
(overshoot) your V2Pro if no termination is used. You might get away
with
the "reduced drive" of the DDR, if possible.
My bet is to simulate it, if you want to minimize the amount of
termination
required.
Kind Regards,
Kristiaan
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On
Behalf Of Anders Frederiksen
Sent: 3-feb-05 23:00
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] DDR-1 termination (short point-to-point)


I'm connecting a lot of DDR1 ram to a FPGA (Virtex2pro). Common=20
schemes recommended is "embedding a DIMM design" (which would be=20
plain stupid imho) and doing a full parallel termination in both ends=20
(typically in 0402). The latter is naturally sensible - but it occurs=20
to be kind of a overkill for ponit-to-point lines of "only" 5cm (~2")=20
or less. Has anyone experience with simpler termination schemes? I=20
mean for standard busses one would rely on slow drivers only...

Cheers,
 Anders



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