FreeLists / si-list / [SI-LIST] Re: Input Clock phase noise and TX eye closurein SERDES

[johndp@xxxxxxxx]

Craig,

thanks for the reply.

Say for the CDR in a FC-AL system, this has a low frequency 3dB point of 
Dbaud/1667 which for a 1.0625Gb/s link is 637KHz. If we combine this with the 
high pass function of the TX PLL we get a bandpass filter. Looking at the noise 
envelope of a good quality source, I can see that it remains relatively flat at 
about 145dBc/Hz above 1MHz, and so above the 3dB point of the TX PLL this is 
being attenuated at 20dB/decade. 

The low frequency point still bothers me. With the break point at 637Khz, the 
filtering effect is approx -36dB@10Khz, -56dB@1KHz, -76db@100Hz. The source 
phase noise is correspondingly -130dBc/Hz@10KHz, -100dBc/Hz@1KHz and  -65dBc/Hz 
@100Hz compared to -145dB/Hz @1MHz. So down to 1KHz the Filter roll off is 
faster than the rise in phase noise, but down at 100Hz, the phase noise is 
increasing faster than the roll off. So I still don't quite see how the lower 
limit is set.


Regards

John

ctwardy@xxxxxxxxxx wrote:
> Hi John;
> The lower limit will be defined by the bandwidth of the clock and data
> recovery (CDR)of the receiver.
> The 10Khz (or 14-20Khz often) lower limit is used as most oscillators
> exhibit a large increase of phase noise below this frequency. Check out any
> phase noise plot of a stable oscillator.
> Any CDR must deal with this.
> Another way to look at it is to compare noise power over various bandwidths.
> Compare the noise in
> The integral from DC to F lowerlimit to the noise in the integral from F
> lowerlimit to F upperlimit.
> It most systems, I believe, that F upperlimit value is important in
> determining the amount of random noise.
> Craig
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
> Behalf Of johndp@xxxxxxxx
> Sent: January 31, 2005 12:36 PM
> To: si-list@xxxxxxxxxxxxx
> Cc: johndp@xxxxxxxx
> Subject: [SI-LIST] Input Clock phase noise and TX eye closurein SERDES
> 
> I'm trying to relate reference clock phase noise to eye closure in a TX
> SERDES application. At this time I'm only interested in this area of the TX
> performance, as I'm trying to specify a clocking scheme for a much larger
> design. Assuming a second order TX PLL I can come up with an expression that
> relates the reference clock phase noise to the transfer characteristic of
> the PLL. However I'm stuck with an intergral to work out the RMS jitter of
> the reference, the upper limit of which is set by the 3dB point of the PLL,
> I'm not sure how to set the lower limit. I've read in a couple of places for
> example ref (1), a figure of 10KHz but can find no analytical basis for this
> figure.
> 
> Any pointers much appreciated
> 
> ref (1) Random Jitter - What Is Really Going On?
> October 22, 2001 - CommsDesign.com 
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