FreeLists / si-list / [SI-LIST] Re: Input Clock phase noise and TX eye closurein SERDES

[john <johndp@xxxxxxxx>]

Sorry I didn't mean to remain anonymous.. just typed ctrl S before I'd 
finished writing:-)

Regards

John

johndp@xxxxxxxx wrote:

>I'm trying to relate reference clock phase noise to eye closure in a TX SERDES 
>application. At this time I'm only interested in this area of the TX 
>performance, as I'm trying to specify a clocking scheme for a much larger 
>design. Assuming a second order TX PLL I can come up with an expression that 
>relates the reference clock phase noise to the transfer characteristic of the 
>PLL. However I'm stuck with an intergral to work out the RMS jitter of the 
>reference, the upper limit of which is set by the 3dB point of the PLL, I'm 
>not sure how to set the lower limit. I've read in a couple of places for 
>example ref (1), a figure of 10KHz but can find no analytical basis for this 
>figure.
>
>
>Any pointers much appreciated
>
>
>ref (1) Random Jitter - What Is Really Going On?
>October 22, 2001 - CommsDesign.com 
>
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