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Thread Index for si-list, 02-2004

[si-list] || [02-2004 Date Index] [02-2004 Thread Index]

  1. [SI-LIST] Re: Traces don't cause EMI - really?, Lee Ritchey
  2. [SI-LIST] Re: SMD capacitor question, Bart Bouma
  3. [SI-LIST] Buried uStrip question, Grasso, Charles
  4. [SI-LIST] Re: Buried uStrip question, Lee Ritchey
  5. [SI-LIST] Re: Stack up for EMI reduction, Ahmad Fallah
  6. [SI-LIST] ESD solution on antenna output, Ian Barrett
  7. [SI-LIST] Re: ESD solution on antenna output, Raymond Anderson
  8. [SI-LIST] Stack up for EMI reduction, plane resonance and u-strip radiation etc etc, Chris Cheng
  9. [SI-LIST] Seeking SI Eng. for 6-12 month project - NC, Steve G
  10. [SI-LIST] trace characteristic impedance, Doug Smith
  11. [SI-LIST] Need Hard drive that works up to 65 deg ?, Steve Rogers
  12. [SI-LIST] Re: ESD solution on antenna output (re-send), Ian Barrett
  13. [SI-LIST] [Fwd: Humidity effects on Rogers R3003], Raymond Anderson
  14. [SI-LIST] Re: Need Hard drive that works up to 65 deg ?, Tom Biggs
  15. [SI-LIST] ESD structure for an inverter, Haritha Chanda
  16. [SI-LIST] What is High K ceramic capacitors?, Zhangkun
  17. [SI-LIST] Questions on PLL response, Parthasarathy Sampath
  18. [SI-LIST] Re: Questions on PLL response, Geoff Stokes
  19. [SI-LIST] Career Opportunity: Bose Corporation Position for a Failure Analysis Engineer, Triolo, Vicky
  20. [SI-LIST] HI, raghu
  21. [SI-LIST] 2-port VNA -> 4-port VNA ?, npischl
  22. [SI-LIST] Re: ESD structure for an inverter, Raymond . Leung
  23. [SI-LIST] Re: 2-port VNA -> 4-port VNA ?, Shi, Wenjun
  24. [SI-LIST] Invitation for workshop on "Parallel Optical Interconnects Inside Electronic Systems", Ronny Bockstaele
  25. [SI-LIST] Socket Material, Rich Peyton
  26. [SI-LIST] Re: Socket Material, Steve Rogers
  27. [SI-LIST] IIP3 analysis with netlists having nport statements, Amitava Bhaduri
  28. [SI-LIST] SI Employment Opportunity, Anil Pannikkat
  29. [SI-LIST] test, jeff . loyer
  30. [SI-LIST] Emission, BRanjul
  31. [SI-LIST] Re: Emission, Kbalasubramanian
  32. [SI-LIST] ground bounce, Santhosh E P
  33. [SI-LIST] IBIS model, Somashekhara Gowda B P
  34. [SI-LIST] Re: New Books, Robert Haller
  35. [SI-LIST] E U R O P E A N I B I S S U M M I T M E E T I N G 2004 - Final Call for Participation+Draft Agenda, Ralf Bruening
  36. [SI-LIST] Re: SIAuditor, arsenault, brian
  37. [SI-LIST] Re: IIP3 analysis with netlists having nport statements, Amitava Bhaduri
  38. [SI-LIST] Re: Stack up for EMI reduction, plane resonance and u-strip radiation etc etc, Chris Cheng
  39. [SI-LIST] Consideration for SSO with transmission line effect, Eric Hsu
  40. [SI-LIST] confusing emissions and immunity, Doug Smith
  41. [SI-LIST] Re: confusing emissions and immunity, Gian YK-r58635
  42. [SI-LIST] Node -1 in SPICE, Gian YK-r58635
  43. [SI-LIST] Hysteresis in SI (Signal Integrity)??, =?big5?b?tF4gpGyqWQ==?=
  44. [SI-LIST] Re: IBIS model, Somashekhara Gowda B P
  45. [SI-LIST] How to select inductor or bead?, Zhangkun
  46. [SI-LIST] Fw: 答复: How to select inductor orbead?, yu . yanfeng
  47. [SI-LIST] Please check this spec. sheet., Inmyung Song
  48. [SI-LIST] Please check this spec. sheet!, 송인명
  49. [SI-LIST] Injected Crosstalk, Moeller, Merrick
  50. [SI-LIST] Re: Hysteresis in SI (Signal Integrity)??, MikonCons
  51. [SI-LIST] Re: How to select inductor or bead?, MikonCons
  52. [SI-LIST] [Fwd: Re: Stack up for EMI reduction,plane resonance and u-s trip radiation etc etc], Raymond Anderson
  53. [SI-LIST] Resent : Hysteresis in SI (Signal Integrity)??, Chris Cheng
  54. [SI-LIST] Re: Stack up for EMI reduction, plane resonance and u-s trip radiation etc etc, Chris Cheng
  55. [SI-LIST] FCC aproval, K. Sankar
  56. [SI-LIST] Industrial Temp FCRAMs (266MHz, CL = 5) and DDRs (266MHz), Long Nguyen
  57. [SI-LIST] LCD Panels - EMC and Shock Mounting, Peter Baxter
  58. [SI-LIST] Re: FCC approval, Steve Rogers
  59. [SI-LIST] Re: FCC aproval, Grasso, Charles
  60. [SI-LIST] ibis check output errors, Alaa Alani
  61. [SI-LIST] Re: ibis check output errors, Muranyi, Arpad
  62. [SI-LIST] Fwd: RE: Re: Stack up for EMI reduction, plane resonance and u-s trip radiation etc etc, steve weir
  63. [SI-LIST] Re: Stack up for EMI reduction, plane resonance and u-s trip radiation etc etc, Istvan NOVAK
  64. [SI-LIST] IBIS QUALITY, Naftali . Refaeli
  65. [SI-LIST] Re: IBIS QUALITY, =?big5?b?SG91S2V2aW4oq0ql/qaoKQ==?=
  66. [SI-LIST] pre-emphasis, sivi.cla@xxxxxxxxx
  67. [SI-LIST] Please tell me your birthday, thudhu
  68. [SI-LIST] Re: pre-emphasis, Brad Griffin
  69. [SI-LIST] Re: Transformer Spice Model, Dr. Edward P. Sayre
  70. [SI-LIST] Re: Please tell me your birthday, Hargin, Bill
  71. [SI-LIST] Re: Stack up for EMI reduction, plane resonance and u-strip r adiation etc etc, Grasso, Charles
  72. [SI-LIST] Re: Stack up for EMI reduction, plane resonance and u-str ip radiation etc etc, Grasso, Charles
  73. [SI-LIST] Looking for SI job, mahamud khandokar
  74. [SI-LIST] survey of 2D field solvers, Eric Bogatin
  75. [SI-LIST] Old Anritsu spectrum analyzer, joan vicent castell
  76. [SI-LIST] Re: Stack up for EMI reduction,plane resonance and u-str ip radiation etc etc, Bart Bouma
  77. [SI-LIST] Re: Stack up for EMI reduction,plane resonance and u-str ip radiation etc etc, Craig Twardy
  78. [SI-LIST] Agenda, European IBIS Summit at DATe 2004 , February the 20th 2004, Ralf Bruening
  79. [SI-LIST] On the effect of solder mask on Zo, Grasso, Charles
  80. [SI-LIST] Re: survey of 2D field solvers, Beal, Weston
  81. [SI-LIST] Re: On the effect of solder mask on Zo, Abe Riazi
  82. [SI-LIST] Re: On the effect of solder mask on Zo - Update, Grasso, Charles
  83. [SI-LIST] Re: Best PDS impedance for package damping, Chris Cheng
  84. [SI-LIST] Re: [Fwd: Humidity effects on Rogers R3003], MikonCons
  85. [SI-LIST] A question, Keren&Meiri
  86. [SI-LIST] carbon fiber pre-preg characteristics?, Brent DeWitt
  87. [SI-LIST] High sample rate A/D., Yoram Porat
  88. [SI-LIST] Re: Stack up for EMI reduction,plane resonance and u-str ipradiation etc etc, Vishram Pandit
  89. [SI-LIST] Switch on differential lines of ethernet, Somashekhara Gowda B P
  90. [SI-LIST] Power dissipation- Ambient temperature, Prasanna R - CTD, Chennai.
  91. [SI-LIST] FW: Digest Number 1005, Thomas Beneken
  92. [SI-LIST] Re: Switch on differential lines of ethernet, Somashekhara Gowda B P
  93. [SI-LIST] Power Calculations, Moeller, Merrick
  94. [SI-LIST] Package, pad, bond, and bond wire parasitic capacitence USB 2.0 HS, eric steimle
  95. [SI-LIST] run Xilinx Hspice models, sivi.cla@xxxxxxxxx
  96. [SI-LIST] Re: Package, pad, bond, and bond wire parasitic capacitence USB 2.0 HS, Lee Ritchey
  97. [SI-LIST] Re: carbon fiber pre-preg characteristics?, Michael Poimboeuf
  98. [SI-LIST] Applications Engineer, Ruth Shepard
  99. [SI-LIST] Applications Engineer Position, Ruth Shepard
  100. [SI-LIST] Call For Papers: EPEP 2004, Raymond Anderson
  101. [SI-LIST] How do you perform a frequency sweep of a differential coupled line model in Hspice ?, Jon Stahl
  102. [SI-LIST] Re: Stack up for EMI reduction,plane resonance and u-str ip radiation etc etc, Chris Cheng
  103. [SI-LIST] Modeling Probe Pins as Connector Model in LineSim, Gian YK-r58635
  104. [SI-LIST] Re: How do you perform a frequency sweep of a differential coupled line model in Hspice ?, Zabinski, Patrick J.
  105. [SI-LIST] Layout Cross Section, Uri Chaplianka
  106. [SI-LIST] Re: How do you perform a frequency sweep of a differential coupled line model in Hspice ?, Muranyi, Arpad
  107. [SI-LIST] Test message, Muranyi, Arpad
  108. [SI-LIST] Re: Test message, Muranyi, Arpad
  109. [SI-LIST] Re: How do you perform a frequency sweep of a differential coupled line model in Hspice ?, Muranyi, Arpad
  110. [SI-LIST] How to do Z(f), Y(f) sweep in Q2D?, bao2 bao
  111. [SI-LIST] Re: Layout Cross Section, Uri Chaplianka
  112. [SI-LIST] R: Layout Cross Section, Guasti Giovanni
  113. [SI-LIST] Re: Separate GND for Analog & Digital, Lee Ritchey
  114. [SI-LIST] .MEAS INSIDE TRAN HSPICE, PRIYATHARSHAN, PATHMANATHAN
  115. [SI-LIST] Solid modelling, Jayaprakash
  116. [SI-LIST] Convergence problem after inserting detailed connector model, Nekrylova, Julia
  117. [SI-LIST] Re: Convergence problem after inserting detailed co nnector model, Geoff Stokes
  118. [SI-LIST] ref for mmic layout, kaustubh bhate
  119. [SI-LIST] Fw: Hai, RAJAPALANI
  120. [SI-LIST] Re: Hai, RAJAPALANI
  121. [SI-LIST] Re: Convergence problem after inserting detailed connector model, Mirmak, Michael
  122. [SI-LIST] FW: Upcoming Training Reminder, Abdulrahman Rafiq
  123. [SI-LIST] need fastcap program, vinay b
  124. [SI-LIST] DQS vs DDR CLOCK TIMING, Sidney S
  125. [SI-LIST] Even and odd mode capacitances and inductances of coupled lines, Leon Wong
  126. [SI-LIST] Re: Even and odd mode capacitances and inductances of coupled lines, Zabinski, Patrick J.
  127. [SI-LIST] Boston area, Impedance and Materials, 02-Mar, Jeff Seeger
  128. [SI-LIST] First Call for IBIS SUMMIT at DesignCon East 2004, Lynne Green
  129. [SI-LIST] Four model types of "single line model" in ICM 1.0, slwu
  130. [SI-LIST] FW: Question: Hetrodyne Mixer ?, Abdulrahman Rafiq
  131. [SI-LIST] PECL lines, Fraiman Edi-BEF012
  132. [SI-LIST] Re: PECL lines, Larry Barnes
  133. [SI-LIST] Access granted to send emails to bob@cambriandesign.com, bob
  134. [SI-LIST] Amkor Job Opening, Grace Hu
  135. [SI-LIST] Re: Four model types of "single line model" in ICM 1.0, Mirmak, Michael
  136. [SI-LIST] alter processing in Berkeley 3f4 spice, Raymond Anderson
  137. [SI-LIST] SPICE module manual, K. Sankar
  138. [SI-LIST] Current mode current stealing simulation by IBIS file, Sogo Hsu
  139. [SI-LIST] Extract/Convert Lumped Spice model to T-line model, Gian YK-r58635
  140. [SI-LIST] Errata list for High-Speed Digital System Design: A Handbook of InterconnectTheory and Design Practices, John Phillips
  141. [SI-LIST] Middle (Star) Termination, Newton, Scott
  142. [SI-LIST] Re: GND Separation for Analog & Digital circuits, John Barnes
  143. [SI-LIST] Re: Extract/Convert Lumped Spice model to T-line model, Hassan O. Ali
  144. [SI-LIST] Re: Current mode current stealing simulation by IBIS file, Muranyi, Arpad
  145. [SI-LIST] Re: Errata list for High-Speed Digital System Design: A Handbook of Interconnect Theory and Design Practices, Hall, Stephen H
  146. [SI-LIST] Re: Middle (Star) Termination, Newton, Scott
  147. [SI-LIST] PowerMesh article available for download, Grasso, Charles
  148. [SI-LIST] IBIS Newbie, ahmad_s03
  149. [SI-LIST] HSPICE question, chen shu
  150. [SI-LIST] Pcad2000/2001 to Protel converter, ahmad_s03
  151. [SI-LIST] How to connect Chassis ground to DGND, Chris Chalmers
  152. [SI-LIST] Re: HSPICE question, Clewell, Craig
  153. [SI-LIST] DC power distribution, Nadolny, Jim
  154. [SI-LIST] Re: DC power distribution, Chan, Michael (Eng Hou)
  155. [SI-LIST] Re: How to connect Chassis ground to DGND, Grasso, Charles
  156. [SI-LIST] FW: Re: How to connect Chassis ground to DGND, Dr. Howard Johnson
  157. [SI-LIST] Signal Integrity Opening at Intel, Oregon, Gardiner, Scott
  158. [SI-LIST] Gigabit Ethernet Magnetics, SI List




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