FreeLists / si-list / [SI-LIST] Re: Traces don't cause EMI - really?

["Lee Ritchey" <leeritchey@xxxxxxxxxxxxx>]

Wow!  This topic keeps coming up.  Wasn't so long ago that we had a very
long exchange where proponents of this notion provided the research papers
that  supported it.  I got copies of all of them and looked for some
objective measurement of the EMI caused by a trace routed on an outer layer
over a plane and then moved below the plane.

None of the papers did such an experiment in a way that could be used to
bet money on.  I pointed out that the real source of EMI from a PCB were
the lead frames of components that stick up from the PCB.  While at Maxtor,
we had this very problem with disc drives.  We fixed the problem by
changing lead frames from PLCCs to QFPs- packages that don't stick up very
far from the PCB.  If you want to see this in action, go to Frys or any
place else that sells stand alone disc drives and look at how the PCBs are
designed.  All of the signal traces are on outside layers and all of the
disc drives comply with CISPRB B.

We used a pedicel of equipment that allowed the PCB to be laid on it and
then scanned to provide a 2D picture of where emission were coming from.  I
cannot remember the name of the tool, but it had a table with a grid on it
on which the PCB was mounted.  The output looked a lot like what one gets
from a thermal mapping tool showing places with higher emissions.  The
sources of EMI were very clear- the IC lead frames.

There is no doubt that when currents flow in planes that voltage gradients
result.  The question is "are they significant compared to other things?"

It is important to distinguish between visible and significant.  Spending
time on things that are visible, but not significant is not good
engineering.  Barring the use of routing vias in most signals is an example
of this.

The available data does not support the claim that signal traces routed
over a plane on an outside layer of a PCB is a significant source of EMI.  
Until an objective test is done to prove it, the available evidence says
that they do not.

If one wants to go down the path of what happens when the plane is split
up, that is another discussion and one that is likely to prove fruitful and
demonstrate that planes should not be split.

Lee


> [Original Message]
> From: Ken Hayden <khayden@xxxxxxxxxxxxxxxxxx>
> To: Grasso, Charles <Charles.Grasso@xxxxxxxxxxxx>
> Cc: si-list@xxxxxxxxxxxxx <si-list@xxxxxxxxxxxxx>
> Date: 1/30/2004 6:57:12 AM
> Subject: [SI-LIST] Re: Traces don't cause EMI - really?
>
> Thanks for reminding me of Dr. Bogatin's presentation, Charles.  I read
it when
> the si-list first pointed it out, and it's a refreshingly clear treatment
of the
> subject.  If I'm not mistaken, the presentation makes the point that EMI
> generated by the plane voltage drop (caused by signal return current) will
> generally dominate over EMI from the current loop formed by the signal
trace and
> its return current.  As I understand it, the effect of that plane drop
would be
> to cause the whole plane to take on an RF voltage, possibly with standing
waves
> (resonances) as discussed elsewhere in this forum.  If that's the case, I
have
> two questions:
> 1. Wouldn't the net effect of adding another ground plane outside such a
trace
> simply be to reduce the ground drop by less than half, as a result of
adding a
> second parallel return plane (that's  coupled to the first plane fairly
> closely)?
> 2. What about skin effect?  I understand that at frequencies of interest
> (hundreds of MHz and up), the skin depth is only a fraction of the
thickness of
> the copper plane.  This implies that the plane voltage drop induced on the
> inside of  an outer plane could not "penetrate" to the outside to
radiate.  By
> extension, if an overall outer ground plane was used, there would be no
plane
> voltage drop detectable on the outside of the plane.  (I know this is
nonsense,
> but I don't know where my logic is failing.)
> -Ken
>
> "Grasso, Charles" wrote:
>
> > Ken  you may be interested in looking at a presentation made by
> > Dr Bogatin that addressed this very subjecy.
> > you can find it at http://www.ieee.org/rmcemc go to the archives
> > and look for the 2003 December meeting.
> >
> > Cheers
> >
> > Best Regards
> > Charles Grasso
> > Senior Compliance Engineer
> > Echostar Communications Corp.
> > Tel:  303-706-5467
> > Fax: 303-799-6222
> > Cell: 303-204-2974
> > Email: charles.grasso@xxxxxxxxxxxx;
> > Email Alternate: chasgrasso@xxxxxxxx
> >
> >
> > -----Original Message-----
> > From: Ken Hayden [mailto:khayden@xxxxxxxxxxxxxxxxxx]
> > Sent: Friday, January 30, 2004 6:00 AM
> > To: MikonCons@xxxxxxx
> > Cc: si-list@xxxxxxxxxxxxx
> > Subject: [SI-LIST] Re: Traces don't cause EMI - really?
> >
> > I read this thread last fall with great interest, and I think I learned
a
> > lot.  But I
> > have an immediate application about which I'm still confused, and could
use
> > some help.
> >
> > This application is for a PCB that will be assembled into a shielded
card
> > cage
> > assembly.  This particular PCB will not have any cables leaving the
shielded
> > enclosure,
> > but any number of other PCBs in this 36-card assembly could have cables
of
> > various
> > geometries and filtering characteristics.  (This is a telecom/datacom
> > application, and
> > the PCBs are line cards with numerous flavors of DSL, Ethernet, POTS,
and
> > digital
> > telecom interfaces.)
> >
> > We have traditionally laid out PCBs for this application with outside
> > planes, and
> > absolutely everthing with any high-frequency content was run on inside
> > signal layers.
> > Using this kind of stackup, and taking many of the usual precautions, we
> > have had good
> > success in building cards that pass FCC class A, and usually class B.
> >
> > In the current (very quick-turn) project, we will be using an embedded
> > microprocessor we
> > haven't used before.  In the interest of building fully functional
boards
> > with good
> > signal and power integrity as quickly as possible, we are considering
> > directly lifting
> > the processor, DDR SDRAM, gigabit GMII, PCI, and HyperTransport artwork
> > section from the
> > microprocessor vendor's evaluation kit artwork, and incorporating the
> > artwork into the
> > rest of our design.
> >
> > It turns out that this evaluation kit is in PCI plug-in board format
> > (clearly intended
> > to run in a desktop PC), and has the following stackup:
> >
> > TOP
> > GND
> > SIG1
> > GND
> > PWR
> > PWR
> > GND
> > SIG2
> > GND
> > BOT
> >
> > This is of course a wonderful stackup for power distribution, but it
> > requires running
> > close to half of the signals on the outside layers, since there are
only two
> > internal
> > signal layers.  The evaluation kit runs many of the DDR SDRAM, PCI, and
GMII
> > traces on
> > the top and bottom layers.  Only clocks and HyperTransport traces seem
to be
> > strictly
> > limited to SIG1 and SIG2.
> >
> > My question is this:  Is this kind of layout likely to radiate
significantly
> > into other
> > boards in the enclosure (relative to a board with more layers, having
added
> > planes
> > outside all signal layers), thereby risking excessive CM currents from
the
> > cables
> > leading from these other boards?  As I have mentioned, we have always
> > believed that it
> > would, and have avoided such a stackup. But I wonder if we've been going
> > overboard and
> > wasting money on extra layers.
> >
> > Ken Hayden
> > Consulting Engineer
> > Integral Access
> >
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