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Thread Index for si-list, 02-2003

[si-list] || [02-2003 Date Index] [02-2003 Thread Index]

  1. [SI-LIST] Where and how the Ground Noise Come from?, wenjie-jack.yu
  2. [SI-LIST] load of a High-impedant I/O on a bus, Nico Fleurinck
  3. [SI-LIST] Re: Where and how the Ground Noise Come from?, cor . coolen
  4. [SI-LIST] IBIS Development Studio, IBIS Development Studio
  5. [SI-LIST] Re: Conductor Ampacity question, Rich Peyton
  6. [SI-LIST] Re: load of a High-impedant I/O on a bus, James_R_Jones
  7. [SI-LIST] Re: Matching impedance, Ingraham, Andrew
  8. [SI-LIST] Re: EMI fixed by flooding?, Lee Ritchey
  9. [SI-LIST] placement of bias resistors on differential traces, FROMMANN,NIELS (HP-Cupertino,ex1)
  10. [SI-LIST] Help - experience with Ansoft "F" dependent sources????, Dr. Edward P. Sayre
  11. [SI-LIST] Re: How accurate is HSPICE's field solver?, Bi Han
  12. [SI-LIST] UN Petition to Stop War- Spread the Peace, Anton Petersen
  13. [SI-LIST] Re: UN Petition to Stop War- Spread the Peace, Ken Patterson
  14. [SI-LIST] Re: Capacitors UNDER a BGA??, Fred U. Rosenberger
  15. [SI-LIST] fanout, Jayaprakash Balachandran
  16. [SI-LIST] Re: fanout, James_R_Jones
  17. [SI-LIST] Buffer for 2.5Gb/s data, Bob Patel
  18. [SI-LIST] New Paper: Low Inductance Measurements, Gary Otonari
  19. [SI-LIST] Simulator, Nico Fleurinck
  20. [SI-LIST] Antw: Simulator, Robert Nowak
  21. [SI-LIST] European IBIS Summit@DATe2003 - 2nd call for participation and presentations, Ralf Bruening
  22. [SI-LIST] LED measurements, KS Lau
  23. [SI-LIST] back plane vs mother board, hoysala2003
  24. [SI-LIST] random vectors, Yoni Tzafrir
  25. [SI-LIST] Re: random vectors, Ray Anderson
  26. [SI-LIST] Current capacity of a Solder Ball, Brian Schieck
  27. [SI-LIST] Re: Current capacity of a Solder Ball, Clewell, Craig
  28. [SI-LIST] Estimation of trace capacitance, Mangipudi, Prasad
  29. [SI-LIST] Re: Estimation of trace capacitance, Ingraham, Andrew
  30. [SI-LIST] UPDATED SI Measurement Class: GTL 260, Gary Otonari
  31. [SI-LIST] Trace width, hariharan
  32. [SI-LIST] RLGC matrices of a differential pair line, Hassan O. Ali
  33. [SI-LIST] testing, bpanos
  34. [SI-LIST] Help..., Manjusha
  35. [SI-LIST] Max operating frequency of LVDS driver, sunil-chandra . kasanyal
  36. [SI-LIST] a bug in hspice, Neo
  37. [SI-LIST] Re: Help..., James_R_Jones
  38. [SI-LIST] Re: a bug in hspice, Ray Anderson
  39. [SI-LIST] RMCEMC Presentation download, Charles Grasso
  40. [SI-LIST] about n-well parameters in standard 0.18um logic cmos process, Bi Han
  41. [SI-LIST] Re: How accurate is HSPICE's field solver? (#2), MikonCons
  42. [SI-LIST] Traces referenced to gnd/power planes in package, Anshuli Goel
  43. [SI-LIST] Need HFSS CPW Solution Example !!help, Bi Han
  44. [SI-LIST] Re: Need HFSS CPW Solution Example !!help, Mroczkowski, Jason
  45. [SI-LIST] LINPAR, bpanos
  46. [SI-LIST] TDR Training and Signal Integrity Papers, Dima Smolyansky
  47. [SI-LIST] Re: Traces referenced to gnd/power planes in package, Loyer, Jeff
  48. [SI-LIST] Re: CPW in HFSS, ask for help, Bi Han
  49. [SI-LIST] Converting Orcad to Ansoft, ttsp
  50. [SI-LIST] Wafer probing on Al pads, Brian Frank
  51. [SI-LIST] Re: Converting Orcad to Ansoft, ttsp
  52. [SI-LIST] dielectric loss question, Peter Arnold
  53. [SI-LIST] Re: dielectric loss question, Bart Bouma
  54. [SI-LIST] Question related to HFSS: Zpi, Zpv, Zvi difference, Bi Han
  55. [SI-LIST] Re: Wafer probing on Al pads, Prairie, Jason F.
  56. [SI-LIST] Re: Question related to HFSS: Zpi, Zpv, Zvi difference, Grasso, Charles
  57. [SI-LIST] FW: Re: Question related to HFSS: Zpi, Zpv, Zvi difference, Fasig, Jonathan L.
  58. [SI-LIST] Re: FW: Re: Question related to HFSS: Zpi, Zpv, Zvi difference, Ray Anderson
  59. [SI-LIST] IBIS I/O model in HSPICE question, Ed Sayre III
  60. [SI-LIST] Re: Question related to HFSS: Zpi, Zpv, Zvi differe nce, Bi Han
  61. [SI-LIST] Audio And Fan Circuits interference, Brahim Koudssi
  62. [SI-LIST] Re: IBIS I/O model in HSPICE question, Ingraham, Andrew
  63. [SI-LIST] Re: I disagree, I liked your SI list posting, Bi Han
  64. [SI-LIST] Mixed Mode S-Parameters for more than one diff pair., Gustavo Blando
  65. [SI-LIST] Re: LINPAR, MikonCons
  66. [SI-LIST] Re: Mixed Mode S-Parameters for more than one diff pair., Bill Beale
  67. [SI-LIST] S-parameter for differential signals in Hspice, Bob Patel
  68. [SI-LIST] Re: S-parameter for differential signals in Hspice, Bill Beale
  69. [SI-LIST] PECL termination technique?, hariharan
  70. [SI-LIST] Re: Audio And Fan Circuits interference, Bart Bouma
  71. [SI-LIST] PECL termination - won't work ?, WALKER, Mark
  72. [SI-LIST] Even and odd impedances, sunil-chandra . kasanyal
  73. [SI-LIST] Re: Even and odd impedances, Grasso, Charles
  74. [SI-LIST] Experienced SI/EMC Engineer Available, SDSIGUY
  75. [SI-LIST] Total impedance of trace, plated holes and connectors, Fitzgerald, Kevin
  76. [SI-LIST] property about symmetrical network, Zhangkun
  77. [SI-LIST] Using of Distributed Package model for simulation, Harjeet Singh Randhawa
  78. [SI-LIST] Controlled Impedance Calculation for a 8-Layer Stack-up, Gaurav Agrawal
  79. [SI-LIST] radiated emi data, Doug Smith
  80. [SI-LIST] HFSS Issue Zpi Zpv (continued..), Bi Han
  81. [SI-LIST] Re: Controlled Impedance Calculation for a 8-Layer Stack-up, Alan Hilton-Nickel
  82. [SI-LIST] Re: PECL termination technique?, john lipsius
  83. [SI-LIST] RMCEMC January Presentation Download available, Charles Grasso
  84. [SI-LIST] Re: Using of Distributed Package model for simulation, Harjeet Singh Randhawa
  85. [SI-LIST] RMCEMC Slide correction, Charles Grasso
  86. [SI-LIST] digital vector, Yoni Tzafrir
  87. [SI-LIST] Resistor in Board, Neu, Thomas
  88. [SI-LIST] FW: Resistor in Board, Fasig, Jonathan L.
  89. [SI-LIST] SERDES with pre-emphasis, Bob Patel
  90. [SI-LIST] New low inductance second level Interconnection (module to card) (SpringLand Grid Array), Jean Audet
  91. [SI-LIST] mux/demux for GIGA Ethernet diff. lines, Edi Fraiman
  92. [SI-LIST] [Fwd: RE: Re: dielectric loss question], Jim G Roberts
  93. [SI-LIST] De-emphasis in 3GIO, Fuentes, Gabriel
  94. [SI-LIST] Re: digital vector, Yoni Tzafrir
  95. [SI-LIST] Hspice and Skin Effect, Patrick Vincent
  96. [SI-LIST] Trace length vs Delay; Trace length vs Rise/Fall time, jagdeep singh
  97. [SI-LIST] Re: mux/demux for GIGA Ethernet diff. lines, jagdeep singh
  98. [SI-LIST] Re: Trace length vs Delay; Trace length vs Rise/Fallti me, Jones, James R
  99. [SI-LIST] off-diagonal resistance and conductance elements, Zabinski, Patrick J.
  100. [SI-LIST] Re: off-diagonal resistance and conductance elements, Bill Beale
  101. [SI-LIST] Re: HFSS Issue Zpi Zpv (continued..), D G
  102. [SI-LIST] Reducing slew rate, John Coupland
  103. [SI-LIST] Low-Temp Twisted pair cable, Roberto Ciaranfi
  104. [SI-LIST] Couplin capacitance, Anshuli Goel
  105. [SI-LIST] Split planes and ground return wires, Godbout, Marc
  106. [SI-LIST] Re: Split planes and ground return wires, James_R_Jones
  107. [SI-LIST] Re: property about symmetrical network, Zhou, Xingling (Mick)
  108. [SI-LIST] Differential TDR in HSPICE, Bob Patel
  109. [SI-LIST] Re: Regarding "unbonded region" in PCB stackup, Loyer, Jeff
  110. [SI-LIST] FW: RE02 cabling problem, pwelling
  111. [SI-LIST] On die SI discussion forum, Jimmy Chiu
  112. [SI-LIST] Compliant pad on pcb, noneza
  113. [SI-LIST] Trace Dimensions ??, Steve Rogers
  114. [SI-LIST] Antw: Trace Dimensions ??, Robert Nowak
  115. [SI-LIST] About uneven loads, venkatesh_iyer
  116. [SI-LIST] Re: Differential TDR in HSPICE, Clewell, Craig
  117. [SI-LIST] Antw: Hyperlynx, Robert Nowak
  118. [SI-LIST] hspice connecting to an ibis component, Yoni Tzafrir
  119. [SI-LIST] Re: Antw: Trace Dimensions ??, Robert Nowak
  120. [SI-LIST] Re: Trace Dimensions ??, Ray Anderson
  121. [SI-LIST] FW: Antw: Hyperlynx, Hargin, Bill
  122. [SI-LIST] SI & EMC certifications, Clyde R. Visser, P.E.
  123. [SI-LIST] Re: SI & EMC certifications, pwelling
  124. [SI-LIST] signal integrity step by step, mbestha
  125. [SI-LIST] Trace's width variant designed on PCB!, Jack W.C. Lin
  126. [SI-LIST] CPCI - PRST#;DEG#;FAL#,INTP,INTS -- GA(4..0) questions, Nico Fleurinck
  127. [SI-LIST] European IBIS Summit@DATe2003 - Agenda + 3rd call for participation and presentations, Ralf Bruening
  128. [SI-LIST] Logic Family with ensured low outputs when no power is there, Harjeet Singh Randhawa
  129. [SI-LIST] DECOUPLING DOUBT, Juan Manuel
  130. [SI-LIST] Re: De-emphasis in 3GIO, Christopher_Brewster
  131. [SI-LIST] PDS Capacitor Mounting Details for Lowest Inductance?, Steve Lund
  132. [SI-LIST] Re: PDS Capacitor Mounting Details for Lowest Inductance?, Mangipudi, Prasad
  133. [SI-LIST] Re: PCI 33Mhz cables., Victor Do
  134. [SI-LIST] Signal integrity positions at NVIDIA (Santa Clara, Ca), Joshua Hasten
  135. [SI-LIST] Shield ground isolation, Kuriakose, Anand
  136. [SI-LIST] ΄πΈ΄: CPCI - PRST#;DEG#;FAL#,INTP,INTS -- GA(4..0) questions, chendla
  137. [SI-LIST] Solder migration during RFIC testing, noneza
  138. [SI-LIST] Re: Solder migration during RFIC testing, 박종규
  139. [SI-LIST] Impedance matching with CPW, kschoi
  140. [SI-LIST] IBIS Models, Eoin Mc Gibney
  141. [SI-LIST] Re: Impedance matching with CPW, Grossman, Brett
  142. [SI-LIST] Re: Shield ground isolation - logic/chassis ground connection, JMurphy
  143. [SI-LIST] Re: Rise-time of Cascaded Lossy T- Lines, Ingraham, Andrew
  144. [SI-LIST] Re: Shield ground isolation, Ye, Xiaoning
  145. [SI-LIST] question about IBIS's V-T curve Scaleing ?, qzheng
  146. [SI-LIST] Termination of un-used clocks, Kuriakose, Anand
  147. [SI-LIST] [Àüüȸ½Å] Impedance matching with CPW, kschoi
  148. [SI-LIST] Software AppCAD, Pang Ning (Peter)
  149. [SI-LIST] Re: Software AppCAD, Pang Ning (Peter)
  150. [SI-LIST] how to simulate with S parameters, Guasti Giovanni
  151. [SI-LIST] WARNING: [NET0099], Alicia Corrales Chanca
  152. [SI-LIST] Re: Termination of un-used clocks, Ingraham, Andrew
  153. [SI-LIST] AW: si-list Digest V3 #56, Thomas Beneken
  154. [SI-LIST] More lossy t-line questions - attenuation per unit length and ln functions, San Miguel, Shane
  155. [SI-LIST] Design of op-amp, Parthasarathy Sampath
  156. [SI-LIST] Re: Maximum Bandwidth in ISM band, Bart Bouma
  157. [SI-LIST] IBIS & Cable, Ched-Chang Chai
  158. [SI-LIST] Guidlines required for high speed PCB design, Iain Lochhead
  159. [SI-LIST] Forked/Sectioned IBIS Package models, Crain, Dan S
  160. [SI-LIST] Transmitter Chip., Gurumurthy, Radhika
  161. [SI-LIST] Re: Guidlines required for high speed PCB design, Subramanya C K
  162. [SI-LIST] SPI 2003 submission deadline, Carla Giachino
  163. [SI-LIST] compact-PCI design for test question, Nico Fleurinck
  164. [SI-LIST] Ground nodes in spice, Fabrizio Zanella
  165. [SI-LIST] 8b/10b program using MATLAB, Wenxin Tang
  166. [SI-LIST] IEEE CPMT Society Phoenix Chapter - March 25 meeting, Sampath K V K
  167. [SI-LIST] Announcement for the FDIP'03 Workshop, Ray Anderson
  168. [SI-LIST] Re: Ground nodes in spice, Fabrizio Zanella
  169. [SI-LIST] HSPICE syntax, Bob Patel
  170. [SI-LIST] Modeling Pre-Emphasis in IBIS, Timothy Coyle
  171. [SI-LIST] European IBIS Summit@DATe2003 - Agenda, Ralf Bruening
  172. [SI-LIST] Re: Guidelines required for high speed PCB design, Mangipudi, Prasad
  173. [SI-LIST] Hspice diff sim, Dorin
  174. [SI-LIST] Coupling THROUGH a plane?, Boris Yost




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