FreeLists / si-list / [SI-LIST] Re: load of a High-impedant I/O on a bus

["Ingraham, Andrew" <Andrew.Ingraham@xxxxxx>]

Input capacitance is usually specified with an I/O buffer in the high
impedance state, because it is more difficult to measure it (and
probably less important) when the buffer is driving.

Input capacitance is also voltage dependent.

If I were you, I would avoid IBIS models if you want to look at how the
capacitance depends on anything.  In most (if not all?) IBIS models, the
capacitance doesn't vary at all, except versus frequency on account of
the package effects.  Stick with SPICE models, and even then, use
suspicion because they might not accurately represent the input
capacitance and how it may vary.  However, unless you are using
extremely high frequencies, it might be good enough.

If you are interested in the total capacitive load, I would guess you
are using rather low frequencies, probably no more than a few tens of
MHz.  Above that, I'd question whether total capacitive load (as in
Cin(total) = Cin(1) + Cin(2) + Cin(3) ) has any relevance.  In any
event, the capacitance of the traces, pads, etc. might exceed that of
the I/Os.

Regards,
Andy



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