FreeLists / si-list / [SI-LIST] load of a High-impedant I/O on a bus

["Nico Fleurinck" <nico.fleurinck@xxxxxxxxxxxx>]

Dear experts,
For my design i need to trade-off the use of a data-bus buffer.
I know that the data bus of the memory chips are three-state I/O's.
But my question is, what is the load of an I/O pin on a bus when the device
is in a high-impedant state?
Does the high impedant state of an I/O pin effects his Cin??
I need to know this because i need to calculate the total amount of
capacitive load on the data bus.
If you know an answer, please let me know.
Best Regards,
Nico


Nico Fleurinck
Junior Design Engineer
VERHAERT Satellites & Platforms
Hogenakkerhoekstraat 21
B-9150 Kruibeke

Tel : +32 3 250.1984
Fax : +32 3 254.1008
e-mail : nico.fleurinck@xxxxxxxxxxxx
Visit us : www.verhaert.com



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