Date Index for si-list, 02-2003

[si-list] || [02-2003 Date Index] [02-2003 Thread Index]

[SI-LIST] Where and how the Ground Noise Come from? - wenjie-jack.yu
[SI-LIST] load of a High-impedant I/O on a bus - Nico Fleurinck
[SI-LIST] Re: Where and how the Ground Noise Come from? - cor . coolen
[SI-LIST] Re: Where and how the Ground Noise Come from? - wenjie-jack.yu
[SI-LIST] IBIS Development Studio - IBIS Development Studio
[SI-LIST] Re: Conductor Ampacity question - Rich Peyton
[SI-LIST] Re: Where and how the Ground Noise Come from? - James_R_Jones
[SI-LIST] Re: load of a High-impedant I/O on a bus - James_R_Jones
[SI-LIST] Re: Where and how the Ground Noise Come from? - Ingraham, Andrew
[SI-LIST] Re: Matching impedance - Ingraham, Andrew
[SI-LIST] Re: load of a High-impedant I/O on a bus - Ingraham, Andrew
[SI-LIST] Re: EMI fixed by flooding? - Lee Ritchey
[SI-LIST] Re: Matching impedance - Bob Patel
[SI-LIST] Re: EMI fixed by flooding? - Martin Euredjian
[SI-LIST] Re: Matching impedance - Betty Luk
[SI-LIST] Re: Matching impedance - Jon Powell
[SI-LIST] Re: Matching impedance - Yibing Tang
[SI-LIST] Re: Matching impedance - Muranyi, Arpad
[SI-LIST] Re: Matching impedance - Betty Luk
[SI-LIST] Re: Matching impedance - Muranyi, Arpad
[SI-LIST] Re: Matching impedance - Betty Luk
[SI-LIST] placement of bias resistors on differential traces - FROMMANN,NIELS (HP-Cupertino,ex1)
[SI-LIST] Re: Matching impedance - Chris Cheng
[SI-LIST] Help - experience with Ansoft "F" dependent sources???? - Dr. Edward P. Sayre
[SI-LIST] Re: Help - experience with Ansoft "F"dependentsources???? - Neeraj Pendse
[SI-LIST] Re: How accurate is HSPICE's field solver? - Bi Han
[SI-LIST] Re: How accurate is HSPICE's field solver? - Bi Han
[SI-LIST] UN Petition to Stop War- Spread the Peace - Anton Petersen
[SI-LIST] Re: UN Petition to Stop War- Spread the Peace - Ken Patterson
[SI-LIST] Re: UN Petition to Stop War- Spread the Peace - obennig
[SI-LIST] Re: UN Petition to Stop War- Spread the Peace - Michael_Greim
[SI-LIST] Re: Capacitors UNDER a BGA?? - Fred U. Rosenberger
[SI-LIST] fanout - Jayaprakash Balachandran
[SI-LIST] Re: fanout - James_R_Jones
[SI-LIST] Re: Capacitors UNDER a BGA?? - cadpro2k
[SI-LIST] Re: UN Petition to Stop War- Spread the Peace - Ray Anderson
[SI-LIST] Re: Capacitors UNDER a BGA?? - Grasso, Charles
[SI-LIST] Buffer for 2.5Gb/s data - Bob Patel
[SI-LIST] Re: How accurate is HSPICE's field solver? - Ray Anderson
[SI-LIST] New Paper: Low Inductance Measurements - Gary Otonari
[SI-LIST] Re: UN Petition to Stop War- Spread the Peace - Greg Benton
[SI-LIST] Simulator - Nico Fleurinck
[SI-LIST] Antw: Simulator - Robert Nowak
[SI-LIST] European IBIS Summit@DATe2003 - 2nd call for participation and presentations - Ralf Bruening
[SI-LIST] LED measurements - KS Lau
[SI-LIST] Re: How accurate is HSPICE's field solver? - Bi Han
[SI-LIST] Re: UN Petition to Stop War- Spread the Peace - Ken Cantrell
[SI-LIST] back plane vs mother board - hoysala2003
[SI-LIST] random vectors - Yoni Tzafrir
[SI-LIST] Re: random vectors - Ed Sayre III
[SI-LIST] Re: random vectors - Ray Anderson
[SI-LIST] Re: back plane vs mother board - John Barnes
[SI-LIST] Re: random vectors - Jon Powell
[SI-LIST] Current capacity of a Solder Ball - Brian Schieck
[SI-LIST] Re: random vectors - Macomson, Wis
[SI-LIST] Re: Current capacity of a Solder Ball - Moses Chan
[SI-LIST] Re: random vectors - Ray Anderson
[SI-LIST] Re: Current capacity of a Solder Ball - Clewell, Craig
[SI-LIST] Re: Current capacity of a Solder Ball - Brian Schieck
[SI-LIST] Re: Current capacity of a Solder Ball - Pat Diao
[SI-LIST] Re: Current capacity of a Solder Ball - steve weir
[SI-LIST] Re: Current capacity of a Solder Ball - Aubrey_Sparkman
[SI-LIST] Re: Current capacity of a Solder Ball - Matt Kaufmann
[SI-LIST] Re: Current capacity of a Solder Ball - Ozgur Misman
[SI-LIST] Broad based lead engineer available (yes, Signal Integrity too) - Dennis Schmitz
[SI-LIST] Estimation of trace capacitance - Mangipudi, Prasad
[SI-LIST] Re: Current capacity of a Solder Ball - Pat Diao
[SI-LIST] Re: Estimation of trace capacitance - Ingraham, Andrew
[SI-LIST] Re: Current capacity of a Solder Ball - Moses Chan
[SI-LIST] Re: Estimation of trace capacitance - Beal, Weston
[SI-LIST] Re: Current capacity of a Solder Ball - Brian Schieck
[SI-LIST] UPDATED SI Measurement Class: GTL 260 - Gary Otonari
[SI-LIST] Re: Current capacity of a Solder Ball - Matt Kaufmann
[SI-LIST] Re: Where and how the Ground Noise Come from? - zhangkun 29902
[SI-LIST] Re: Estimation of trace capacitance - Nico Fleurinck
[SI-LIST] Trace width - hariharan
[SI-LIST] RLGC matrices of a differential pair line - Hassan O. Ali
[SI-LIST] Re: RLGC matrices of a differential pair line - Dima Smolyansky
[SI-LIST] Re: How accurate is HSPICE's field solver? - Matthew Herndon
[SI-LIST] Re: RLGC matrices of a differential pair line - Steve Corey
[SI-LIST] Re: How accurate is HSPICE's field solver? - Scott McMorrow
[SI-LIST] Re: How accurate is HSPICE's field solver? - Pat Diao
[SI-LIST] Re: How accurate is HSPICE's field solver? - Scott McMorrow
[SI-LIST] testing - bpanos
[SI-LIST] testing - Tae-Sik Cheung
[SI-LIST] Help... - Manjusha
[SI-LIST] Max operating frequency of LVDS driver - sunil-chandra . kasanyal
[SI-LIST] a bug in hspice - Neo
[SI-LIST] Re: Help... - James_R_Jones
[SI-LIST] Re: a bug in hspice - Ray Anderson
[SI-LIST] Re: Help... - Issa, Elie
[SI-LIST] Re: Help... - James_R_Jones
[SI-LIST] Re: How accurate is HSPICE's field solver? - Michael Kurten
[SI-LIST] RMCEMC Presentation download - Charles Grasso
[SI-LIST] Re: a bug in hspice - Neo
[SI-LIST] Re: Help... - =?big5?b?pEK9br1k?=
[SI-LIST] about n-well parameters in standard 0.18um logic cmos process - Bi Han
[SI-LIST] Re: How accurate is HSPICE's field solver? - MikonCons
[SI-LIST] Re: How accurate is HSPICE's field solver? (#2) - MikonCons
[SI-LIST] Max operating frequency of LVDS driver - Raymond . Leung
[SI-LIST] Traces referenced to gnd/power planes in package - Anshuli Goel
[SI-LIST] Need HFSS CPW Solution Example !!help - Bi Han
[SI-LIST] Re: Need HFSS CPW Solution Example !!help - Bi Han
[SI-LIST] Re: Need HFSS CPW Solution Example !!help - Mroczkowski, Jason
[SI-LIST] Re: Help... - Jones, James R
[SI-LIST] LINPAR - bpanos
[SI-LIST] Re: Traces referenced to gnd/power planes in package - Vinu Arumugham
[SI-LIST] TDR Training and Signal Integrity Papers - Dima Smolyansky
[SI-LIST] Re: Traces referenced to gnd/power planes in package - Loyer, Jeff
[SI-LIST] Re: Need HFSS CPW Solution Example !!help - Bi Han
[SI-LIST] Re: CPW in HFSS, ask for help - Bi Han
[SI-LIST] Re: Matching impedance - Muranyi, Arpad
[SI-LIST] Converting Orcad to Ansoft - ttsp
[SI-LIST] Re: Converting Orcad to Ansoft - Michael Khusid
[SI-LIST] Wafer probing on Al pads - Brian Frank
[SI-LIST] Re: Converting Orcad to Ansoft - ttsp
[SI-LIST] Re: Converting Orcad to Ansoft - Anil Pannikkat
[SI-LIST] Re: about n-well parameters in standard 0.18um logic cmosprocess - Sandy Taylor
[SI-LIST] Re: a bug in hspice - Ray Anderson
[SI-LIST] dielectric loss question - Peter Arnold
[SI-LIST] Re: Help... - MikonCons
[SI-LIST] Re: a bug in hspice - Ray Anderson
[SI-LIST] Re: Wafer probing on Al pads - Bi Han
[SI-LIST] Re: Wafer probing on Al pads - Gary Otonari
[SI-LIST] Re: Traces referenced to gnd/power planes in package - Jim G Roberts
[SI-LIST] Re: dielectric loss question - Mike LaBonte
[SI-LIST] Re: dielectric loss question - Jim G Roberts
[SI-LIST] Re: dielectric loss question - Bart Bouma
[SI-LIST] Question related to HFSS: Zpi, Zpv, Zvi difference - Bi Han
[SI-LIST] Re: dielectric loss question - chen, jinhua
[SI-LIST] Re: dielectric loss question - Harvey, Wilbur
[SI-LIST] Re: Wafer probing on Al pads - Prairie, Jason F.
[SI-LIST] Re: Question related to HFSS: Zpi, Zpv, Zvi difference - Grasso, Charles
[SI-LIST] Re: Question related to HFSS: Zpi, Zpv, Zvi difference - Loyer, Jeff
[SI-LIST] Re: CPW in HFSS, ask for help - Chandrasekhar Arun
[SI-LIST] FW: Re: Question related to HFSS: Zpi, Zpv, Zvi difference - Fasig, Jonathan L.
[SI-LIST] Re: FW: Re: Question related to HFSS: Zpi, Zpv, Zvi difference - Richard A. Schumacher
[SI-LIST] Re: FW: Re: Question related to HFSS: Zpi, Zpv, Zvi difference - Ray Anderson
[SI-LIST] Re: FW: Re: Question related to HFSS: Zpi, Zpv, Zvi difference - Ray Anderson
[SI-LIST] Re: FW: Re: Question related to HFSS: Zpi, Zpv, Zvi difference - Kai, Francis
[SI-LIST] Re: FW: Re: Question related to HFSS: Zpi, Zpv, Zvi difference - Ray Anderson
[SI-LIST] IBIS I/O model in HSPICE question - Ed Sayre III
[SI-LIST] Re: IBIS I/O model in HSPICE question - David Fogel
[SI-LIST] Re: tools questions on the reflector - steve weir
[SI-LIST] Re: FW: Re: Question related to HFSS: Zpi, Zpv, Zvi difference - Jon Powell
[SI-LIST] Re: Matching impedance - john lipsius
[SI-LIST] Re: IBIS I/O model in HSPICE question - Todd Westerhoff
[SI-LIST] Re: IBIS I/O model in HSPICE question - Mike LaBonte
[SI-LIST] Re: Question related to HFSS: Zpi, Zpv, Zvi difference - Bi Han
[SI-LIST] Re: CPW in HFSS, ask for help - D G
[SI-LIST] Re: Question related to HFSS: Zpi, Zpv, Zvi difference - Bi Han
[SI-LIST] Re: Question related to HFSS: Zpi, Zpv, Zvi difference - ZL e-Studio
[SI-LIST] Re: Question related to HFSS: Zpi, Zpv, Zvi differe nce - Bi Han
[SI-LIST] Audio And Fan Circuits interference - Brahim Koudssi
[SI-LIST] Re: IBIS I/O model in HSPICE question - Ingraham, Andrew
[SI-LIST] Re: I disagree, I liked your SI list posting - Bi Han
[SI-LIST] Mixed Mode S-Parameters for more than one diff pair. - Gustavo Blando
[SI-LIST] Re: IBIS I/O model in HSPICE question - Jon Powell
[SI-LIST] Re: Audio And Fan Circuits interference - Jon Powell
[SI-LIST] Re: LINPAR - MikonCons
[SI-LIST] Re: Question related to HFSS: Zpi, Zpv, Zvi difference - Carlos Moll
[SI-LIST] Re: Mixed Mode S-Parameters for more than one diff pair. - Bill Beale
[SI-LIST] Re: Audio And Fan Circuits interference - steve weir
[SI-LIST] Re: Audio And Fan Circuits interference - Brahim Koudssi
[SI-LIST] S-parameter for differential signals in Hspice - Bob Patel
[SI-LIST] Re: S-parameter for differential signals in Hspice - Bill Beale
[SI-LIST] Re: S-parameter for differential signals in Hspice - Mirmak, Michael
[SI-LIST] Re: S-parameter for differential signals in Hspice - Bob Patel
[SI-LIST] PECL termination technique? - hariharan
[SI-LIST] Re: Audio And Fan Circuits interference - Bart Bouma
[SI-LIST] PECL termination - won't work ? - WALKER, Mark
[SI-LIST] Re: Audio And Fan Circuits interference - Steve Rogers
[SI-LIST] Re: PECL termination technique? - john lipsius
[SI-LIST] Re: PECL termination technique? - john lipsius
[SI-LIST] Re: S-parameter for differential signals in Hspice - Clewell, Craig
[SI-LIST] Even and odd impedances - sunil-chandra . kasanyal
[SI-LIST] Re: Even and odd impedances - Martyn Gaudion
[SI-LIST] Re: Even and odd impedances - X2Y
[SI-LIST] Re: Audio And Fan Circuits interference - Boris Yost
[SI-LIST] Re: Even and odd impedances - Grasso, Charles
[SI-LIST] Re: Even and odd impedances - Loyer, Jeff
[SI-LIST] Experienced SI/EMC Engineer Available - SDSIGUY
[SI-LIST] Re: Audio And Fan Circuits interference - Brahim Koudssi
[SI-LIST] Re: dielectric loss question - Jim G Roberts
[SI-LIST] Re: Harvy Wilbur dielectric loss question - Jim G Roberts
[SI-LIST] Re: Even and odd impedances - Ray Anderson
[SI-LIST] Total impedance of trace, plated holes and connectors - Fitzgerald, Kevin
[SI-LIST] Re: Total impedance of trace, plated holes and connectors - Martyn Gaudion
[SI-LIST] property about symmetrical network - Zhangkun
[SI-LIST] Re: Even and odd impedances - john lipsius
[SI-LIST] Re: Even and odd impedances - john lipsius
[SI-LIST] Using of Distributed Package model for simulation - Harjeet Singh Randhawa
[SI-LIST] Controlled Impedance Calculation for a 8-Layer Stack-up - Gaurav Agrawal
[SI-LIST] Re: Controlled Impedance Calculation for a 8-Layer Stack-up - Jon Powell
[SI-LIST] Re: PECL termination - won't work ? - hariharan
[SI-LIST] Re: PECL termination technique? - hariharan
[SI-LIST] Re: Even and odd impedances - john lipsius
[SI-LIST] Re: PECL termination technique? - john lipsius
[SI-LIST] radiated emi data - Doug Smith
[SI-LIST] HFSS Issue Zpi Zpv (continued..) - Bi Han
[SI-LIST] Re: Audio And Fan Circuits interference - Martin Euredjian
[SI-LIST] Re: Controlled Impedance Calculation for a 8-Layer Stack-up - Alan Hilton-Nickel
[SI-LIST] Re: PECL termination technique? - john lipsius
[SI-LIST] RMCEMC January Presentation Download available - Charles Grasso
[SI-LIST] Re: Using of Distributed Package model for simulation - Harjeet Singh Randhawa
[SI-LIST] RMCEMC Slide correction - Charles Grasso
[SI-LIST] Regarding "unbonded region" in PCB stackup - Siva kumar
[SI-LIST] digital vector - Yoni Tzafrir
[SI-LIST] Resistor in Board - Neu, Thomas
[SI-LIST] FW: Resistor in Board - Fasig, Jonathan L.
[SI-LIST] SERDES with pre-emphasis - Bob Patel
[SI-LIST] New low inductance second level Interconnection (module to card) (SpringLand Grid Array) - Jean Audet
[SI-LIST] Re: digital vector - Tadashi Arai
[SI-LIST] mux/demux for GIGA Ethernet diff. lines - Edi Fraiman
[SI-LIST] Re: Even and odd impedances - S.Balasubramanian
[SI-LIST] [Fwd: RE: Re: dielectric loss question] - Jim G Roberts
[SI-LIST] Re: SERDES with pre-emphasis - Mike Khusid
[SI-LIST] De-emphasis in 3GIO - Fuentes, Gabriel
[SI-LIST] Re: digital vector - Yoni Tzafrir
[SI-LIST] Re: digital vector - Yoni Tzafrir
[SI-LIST] Hspice and Skin Effect - Patrick Vincent
[SI-LIST] Trace length vs Delay; Trace length vs Rise/Fall time - jagdeep singh
[SI-LIST] Re: mux/demux for GIGA Ethernet diff. lines - jagdeep singh
[SI-LIST] Re: Trace length vs Delay; Trace length vs Rise/Fallti me - Jones, James R
[SI-LIST] off-diagonal resistance and conductance elements - Zabinski, Patrick J.
[SI-LIST] Re: off-diagonal resistance and conductance elements - Bill Beale
[SI-LIST] Re: off-diagonal resistance and conductance elements - Ray Anderson
[SI-LIST] Re: off-diagonal resistance and conductance elements - Dunbar, Tony
[SI-LIST] Re: HFSS Issue Zpi Zpv (continued..) - D G
[SI-LIST] Reducing slew rate - John Coupland
[SI-LIST] Re: off-diagonal resistance and conductance elements - Raj Raghuram
[SI-LIST] Re: off-diagonal resistance and conductanceelements - Neeraj Pendse
[SI-LIST] Re: off-diagonal resistance and conductance elements - Zabinski, Patrick J.
[SI-LIST] Low-Temp Twisted pair cable - Roberto Ciaranfi
[SI-LIST] Couplin capacitance - Anshuli Goel
[SI-LIST] Re: off-diagonal resistance and conductance elements - Anshuli Goel
[SI-LIST] Re: off-diagonal resistance and conductance elements - D G
[SI-LIST] Split planes and ground return wires - Godbout, Marc
[SI-LIST] Re: Split planes and ground return wires - James_R_Jones
[SI-LIST] Re: property about symmetrical network - Zhou, Xingling (Mick)
[SI-LIST] Re: off-diagonal resistance and conductance elements - Zabinski, Patrick J.
[SI-LIST] Re: Low-Temp Twisted pair cable - Drew
[SI-LIST] Re: off-diagonal resistance and conductance elements - Bill Beale
[SI-LIST] Re: off-diagonal resistance and conductance elements - Fred Balistreri
[SI-LIST] Re: off-diagonal resistance and conductance elements - Steve Corey
[SI-LIST] Re: Split planes and ground return wires - Ingraham, Andrew
[SI-LIST] Re: off-diagonal resistance and conductance elements - Ray Anderson
[SI-LIST] Re: off-diagonal resistance and conductance elements - Issa, Elie
[SI-LIST] Re: Split planes and ground return wires - Brown, Mike (AUS)
[SI-LIST] Differential TDR in HSPICE - Bob Patel
[SI-LIST] Re: off-diagonal resistance and conductance elements - Luca Giacotto
[SI-LIST] Re: Regarding "unbonded region" in PCB stackup - Loyer, Jeff
[SI-LIST] Re: Split planes and ground return wires - pwelling
[SI-LIST] Re: off-diagonal resistance and conductanceelements - Neeraj Pendse
[SI-LIST] FW: RE02 cabling problem - pwelling
[SI-LIST] Re: Regarding "unbonded region" in PCB stackup - pwelling
[SI-LIST] On die SI discussion forum - Jimmy Chiu
[SI-LIST] Compliant pad on pcb - noneza
[SI-LIST] Re: On die SI discussion forum - Charles Grasso
[SI-LIST] Trace Dimensions ?? - Steve Rogers
[SI-LIST] Antw: Trace Dimensions ?? - Robert Nowak
[SI-LIST] Re: Split planes and ground return wires - Adrian Udenze - Sun Uk - NSUK - Signal Integrity Engineer
[SI-LIST] Re: Trace length vs Delay; Trace length vs Rise/Fallti me - Jim G Roberts
[SI-LIST] About uneven loads - venkatesh_iyer
[SI-LIST] Re: Differential TDR in HSPICE - Clewell, Craig
[SI-LIST] Re: Trace Dimensions ?? - Jeremy W. Webb
[SI-LIST] Antw: Hyperlynx - Robert Nowak
[SI-LIST] Re: Compliant pad on pcb - Nick Langston
[SI-LIST] hspice connecting to an ibis component - Yoni Tzafrir
[SI-LIST] Re: Antw: Trace Dimensions ?? - Robert Nowak
[SI-LIST] Re: Trace Dimensions ?? - Ken Cantrell
[SI-LIST] Re: Split planes and ground return wires - Dr. Howard Johnson
[SI-LIST] Re: Trace Dimensions ?? - Ray Anderson
[SI-LIST] Re: Split planes and ground return wires - Charles Sweeney
[SI-LIST] Re: Split planes and ground return wires - Godbout, Marc
[SI-LIST] Re: Split planes and ground return wires - Ingraham, Andrew
[SI-LIST] Re: Split planes and ground return wires - Godbout, Marc
[SI-LIST] FW: Antw: Hyperlynx - Hargin, Bill
[SI-LIST] Re: Split planes and ground return wires - Dr. Howard Johnson
[SI-LIST] SI & EMC certifications - Clyde R. Visser, P.E.
[SI-LIST] Re: SI & EMC certifications - pwelling
[SI-LIST] signal integrity step by step - mbestha
[SI-LIST] Trace's width variant designed on PCB! - Jack W.C. Lin
[SI-LIST] CPCI - PRST#;DEG#;FAL#,INTP,INTS -- GA(4..0) questions - Nico Fleurinck
[SI-LIST] European IBIS Summit@DATe2003 - Agenda + 3rd call for participation and presentations - Ralf Bruening
[SI-LIST] Logic Family with ensured low outputs when no power is there - Harjeet Singh Randhawa
[SI-LIST] DECOUPLING DOUBT - Juan Manuel
[SI-LIST] Re: DECOUPLING DOUBT - Otto
[SI-LIST] Re: De-emphasis in 3GIO - Christopher_Brewster
[SI-LIST] Re: De-emphasis in 3GIO - Ray Anderson
[SI-LIST] PDS Capacitor Mounting Details for Lowest Inductance? - Steve Lund
[SI-LIST] Re: De-emphasis in 3GIO - Dr. Edward P. Sayre
[SI-LIST] Re: PDS Capacitor Mounting Details for Lowest Inductance? - Mangipudi, Prasad
[SI-LIST] Re: De-emphasis in 3GIO - Ed Priest
[SI-LIST] Re: PCI 33Mhz cables. - Victor Do
[SI-LIST] Re: Logic Family with ensured low outputs when no power isthere - Mike Brown
[SI-LIST] Re: PDS Capacitor Mounting Details for Lowest Inductance? - Tom Biggs
[SI-LIST] Signal integrity positions at NVIDIA (Santa Clara, Ca) - Joshua Hasten
[SI-LIST] Shield ground isolation - Kuriakose, Anand
[SI-LIST] Re: Couplin capacitance - Abe Riazi
[SI-LIST] Re: PDS Capacitor Mounting Details for Lowest Inductance? - H. Selfridge
[SI-LIST] Shield ground isolation - Kuriakose, Anand
[SI-LIST] Re: Shield ground isolation - Paul Young
[SI-LIST] ΄πΈ΄: CPCI - PRST#;DEG#;FAL#,INTP,INTS -- GA(4..0) questions - chendla
[SI-LIST] Solder migration during RFIC testing - noneza
[SI-LIST] Re: Shield ground isolation - steve weir
[SI-LIST] Re: Solder migration during RFIC testing - 박종규
[SI-LIST] Impedance matching with CPW - kschoi
[SI-LIST] IBIS Models - Eoin Mc Gibney
[SI-LIST] Re: Shield ground isolation - Ken Cantrell
[SI-LIST] Re: De-emphasis in 3GIO - Bill Beale
[SI-LIST] Re: Shield ground isolation - Val Mandrusov
[SI-LIST] Re: Impedance matching with CPW - Bi Han
[SI-LIST] Re: Logic Family with ensured low outputs when no poweris there - Lieby David
[SI-LIST] Re: Impedance matching with CPW - Drew
[SI-LIST] Re: Impedance matching with CPW - Grossman, Brett
[SI-LIST] Re: Shield ground isolation - logic/chassis ground connection - JMurphy
[SI-LIST] Re: Rise-time of Cascaded Lossy T- Lines - Ingraham, Andrew
[SI-LIST] Re: Impedance matching with CPW - Martyn Gaudion
[SI-LIST] Re: PDS Capacitor Mounting Details for Lowest Inductance? - Steve Lund
[SI-LIST] Re: Audio And Fan Circuits interference - Brahim Koudssi
[SI-LIST] Re: Impedance matching with CPW - Bi Han
[SI-LIST] Re: Impedance matching with CPW - Bi Han
[SI-LIST] Re: Shield ground isolation - Ye, Xiaoning
[SI-LIST] question about IBIS's V-T curve Scaleing ? - qzheng
[SI-LIST] Re: Solder migration during RFIC testing - noneza
[SI-LIST] Termination of un-used clocks - Kuriakose, Anand
[SI-LIST] Re: Termination of un-used clocks - Tom Dagostino
[SI-LIST] [Àüüȸ½Å] Impedance matching with CPW - kschoi
[SI-LIST] Re: Termination of un-used clocks - Bi Han
[SI-LIST] Re: Couplin capacitance - Jeremy Plunkett
[SI-LIST] Software AppCAD - Pang Ning (Peter)
[SI-LIST] Re: Software AppCAD - Nico Fleurinck
[SI-LIST] Re: Software AppCAD - Pang Ning (Peter)
[SI-LIST] how to simulate with S parameters - Guasti Giovanni
[SI-LIST] Re: Rise-time of Cascaded Lossy T- Lines - Hirshtal Itzhak
[SI-LIST] WARNING: [NET0099] - Alicia Corrales Chanca
[SI-LIST] Re: Software AppCAD - herbert_lage
[SI-LIST] Re: Termination of un-used clocks - steve weir
[SI-LIST] Re: Termination of un-used clocks - Ingraham, Andrew
[SI-LIST] AW: si-list Digest V3 #56 - Thomas Beneken
[SI-LIST] More lossy t-line questions - attenuation per unit length and ln functions - San Miguel, Shane
[SI-LIST] Re: how to simulate with S parameters - Dima Smolyansky
[SI-LIST] Re: Rise-time of Cascaded Lossy T- Lines - Dr. Howard Johnson
[SI-LIST] Maximum Bandwidth in ISM band - Himanshu Arora
[SI-LIST] Design of op-amp - Parthasarathy Sampath
[SI-LIST] Re: Couplin capacitance - Abe Riazi
[SI-LIST] Re: Maximum Bandwidth in ISM band - Bart Bouma
[SI-LIST] IBIS & Cable - Ched-Chang Chai
[SI-LIST] Guidlines required for high speed PCB design - Iain Lochhead
[SI-LIST] Re: IBIS & Cable - Subramanya C K
[SI-LIST] Re: IBIS & Cable - Jon Powell
[SI-LIST] Re: IBIS & Cable - Hugo-(gcn)
[SI-LIST] Forked/Sectioned IBIS Package models - Crain, Dan S
[SI-LIST] Ferrite filter - Silvano Bettinzana
[SI-LIST] Transmitter Chip. - Gurumurthy, Radhika
[SI-LIST] Re: IBIS & Cable - Subramanya C K
[SI-LIST] Re: Guidlines required for high speed PCB design - Subramanya C K
[SI-LIST] SPI 2003 submission deadline - Carla Giachino
[SI-LIST] compact-PCI design for test question - Nico Fleurinck
[SI-LIST] Ground nodes in spice - Fabrizio Zanella
[SI-LIST] 8b/10b program using MATLAB - Wenxin Tang
[SI-LIST] Re: Ground nodes in spice - Jon Powell
[SI-LIST] Re: Ground nodes in spice - Robert Haller
[SI-LIST] Re: how to simulate with S parameters - Raj Raghuram
[SI-LIST] IEEE CPMT Society Phoenix Chapter - March 25 meeting - Sampath K V K
[SI-LIST] Re: Ground nodes in spice - Scott McMorrow
[SI-LIST] Announcement for the FDIP'03 Workshop - Ray Anderson
[SI-LIST] Re: how to simulate with S parameters - SiWave
[SI-LIST] Re: how to simulate with S parameters - Bob Patel
[SI-LIST] Re: how to simulate with S parameters - Fred Balistreri
[SI-LIST] Re: compact-PCI design for test question - Georg Ramsch
[SI-LIST] Re: Ground nodes in spice - Fabrizio Zanella
[SI-LIST] Re: Ground nodes in spice - Scott McMorrow
[SI-LIST] HSPICE syntax - Bob Patel
[SI-LIST] Re: Guidlines required for high speed PCB design - Subramanya C K
[SI-LIST] Modeling Pre-Emphasis in IBIS - Timothy Coyle
[SI-LIST] Re: Modeling Pre-Emphasis in IBIS - Jon Powell
[SI-LIST] Re: how to simulate with S parameters - Dohn V. Salvador
[SI-LIST] European IBIS Summit@DATe2003 - Agenda - Ralf Bruening
[SI-LIST] Re: Guidelines required for high speed PCB design - Mangipudi, Prasad
[SI-LIST] Re: HSPICE syntax - Tracy Barclay
[SI-LIST] Hspice diff sim - Dorin
[SI-LIST] Coupling THROUGH a plane? - Boris Yost
[SI-LIST] Re: Coupling THROUGH a plane? - Scott McMorrow
[SI-LIST] Re: Coupling THROUGH a plane? - Paul Levin