FreeLists / si-list / [SI-LIST] Re: rise time performance

[Fred Balistreri <fred@xxxxxxxxxxxxx>]

There was no capacitor in the original posting. The case was
ideal, meaning voltage source, lossless transmission lines and
resistance. Under those conditions there will be no tr/tf 
degradation or change except that relection and the final voltage
levels may be different. I am not saying that the ideal case is
in any way realistic but it is theoriticaly correct. Storage
elements and/or copper losses changes the situation. Therefore
I disagree with your rc circuit statements. 

Best Regards,

"Muranyi, Arpad" wrote:
> 
> Since I received a couple of private messages disputing
> what I stated, I feel an HSPICE example may be helpful
> to illustrate what I said (see below).  The waveform at
> nodes RCV1 and RCV2 are identical (until the reflection
> starts kicking in).  Changing the resistor and impedance
> values from 30 to 50 to 70 Ohms will change the edge rate
> seen at the capacitor (which represents the input of the
> receiver).
> 
> Arpad Muranyi
> Intel Corporation
> 
> RC circuit
> **********************************************************************
> .TRAN 1.0ps 10.0ns  SWEEP  Rval  LIN  3 30 70
> .OPTIONS POST=1 POST_VERSION=9007
> .param Rval=50
> **********************************************************************
> Vpls1  Pls1  0  PULSE  (0.0V 1.0V 3.4ns 1.0ps 1.0ps 10.00ns 20.0ns)
> Vpls2  Pls2  0  PULSE  (0.0V 0.5V 1.0ns 1.0ps 1.0ps 10.00ns 20.0ns)
> **********************************************************************
> R1 Pls1 Rcv1 R=Rval
> C1 Rcv1 0    C=10.0pF
> *
> X1 Pls2 Rcv2  Zd_lineW  LENGTH=12  Zo=Rval  DELAY=0.2
> C2 Rcv2 0     C=10.0pF
> **********************************************************************
> **********************************************************************
> **********************************************************************
> ***                                                                ***
> ***                   Intel SPICE Models                           ***
> ***                                                                ***
> **********************************************************************
> **********************************************************************
> * Filename: Zd_lineW.INC                                             *
> * Version:  1.1                                                      *
> * Call As:  Xxxx in out Zd_lineW                                     *
> *           + LENGTH=x Zo=x DELAY=x                                  *
> *                                                                    *
> * Notes:    Zd_lineW is a single conductor microstrip PCB trace model*
> *           with an assumed SPICE node 0 as the ground return.       *
> *           The input parameters are the impedance of the trace and  *
> *           the propagation delay of the wave.                       *
> *                                                                    *
> *           LENGTH  = length of trace (in inches)                    *
> *           Zo      = trace impedance (in Ohms)                      *
> *           DELAY   = propagation delay (in ns/in)                   *
> *                                                                    *
> * Usage of this subcircuit assumes HSPICE 97.2.1 or higher.          *
> **********************************************************************
> .SUBCKT Zd_lineW in1 out1
> +  LENGTH= 1  Zo= 50  DELAY= 0.200
> *
> W in1 0 out1 0
> + N= 1  Umodel= Wzd_line  L=  '0.0254*LENGTH'
> *
> .MODEL Wzd_line
> +  U  LEVEL= 3  PLEV= 1  ELEV= 2  LLEV= 0  NL= 1
> +  l11= '(DELAY*1e-9*Zo)/0.0254'
> +  cr1= '(DELAY*1e-9)/(Zo*0.0254)'
> +  r11= 0
> +  rrr= 0
> .ENDS
> **********************************************************************
> *    END OF FILE:       Zd_lineW.INC                                 *
> **********************************************************************
> .END
> **********************************************************************
> -----Original Message-----
> From: Muranyi, Arpad
> Sent: Thursday, January 31, 2002 4:53 PM
> To: si
> Subject: RE: [SI-LIST] Re: rise time performance
> 
> Guys,
> 
> It is much simpler than you may think.  Imagine that your
> driver is an ideal switch, and the transmission line is
> a Thevenin resistor connecting the driver with the load
> capacitor.  What do you get?  A simple RC circuit.  Guess
> what happens when you change the value of the Thevenin
> resistor?  The RC constant changes as well as the slope
> of the (exponential) curve.  The same thing happens with
> your original circuit.  No need for any RF explanation...
> 
> Arpad Muranyi
> Intel Coropraiton
> ==========================================================
> 
> -----Original Message-----
> From: Loyer, Jeff W [mailto:jeff.w.loyer@xxxxxxxxx]
> Sent: Thursday, January 31, 2002 10:10 AM
> To: 'jleung@xxxxxxxxxxxxxxx'; si
> Subject: [SI-LIST] Re: rise time performance
> 
> Well, I kept waiting for someone else to add enlightenment, but I guess
> everyone else is busy reminiscing about the good 'ol days when college made
> REAL engineers :-)
> 
> In the S.I. classes I've attended, I have never heard of this phenomena.  I
> duplicated your results (risetime increasing by merely going through an
> impedance variation).  In retrospect, it might have been predicted (RF folks
> have been making cool filters out of structures on PCBs for years), but I
> don't think it's "intuitively obvious to the casual observer".   I'm
> surprised an RF person didn't respond to the question with a clear
> explanation (hint, hint).
> 
> Meanwhile, you might want to look at the same simulation in the frequency
> domain (I did).  That same impedance discontinuity has clearly different
> effects, dependent on frequency.
> 
> Jeff Loyer
> 
> -----Original Message-----
> From: Jason D Leung [mailto:jleung@xxxxxxxxxxxxxxx]
> Sent: Monday, January 28, 2002 6:08 AM
> To: si
> Subject: [SI-LIST] Re: rise time performance
> 
> Hi all,
> I have found something interesting while I was doing some simulation and
> would like to see if there is anyone out there also see this.
> I have found that using different impedance for a transmission line, I
> can obtain different rise time at the receiver.
> Let say I have a simple net with a driver -> 60 ohms tline-> 35 ohm
> stripline(this is the part I am going to change for the experiment)->
> receiver
> and the rise time for the driver is 0.25ns. For a 35 ohm stripline I can
> achieve a rise time of 0.4 ns at the output, and if we replace the 35
> ohm stripline with a 85 ohm stripline I can achieve a rise time of 0.3
> ns at the output. Moreover for a 15 ohm stripline I can achieve a rise
> time of 0.68 ns at the output.
> For my limited knowledge I can understand if I have a difference in
> impedance along the net, I am going to get different
> overshoot/undershoot since we have a different reflection coefficient,
> but I am having some probelms in understanding why we can achieve a
> different rise time with different impedance.
> Is there any kind soul out there, that can explain this phenomenon to
> me?
> thanks in advance
> Jason Leung
> 
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-- 
Fred Balistreri
fred@xxxxxxxxxxxxx

http://www.apsimtech.com
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