[SI-LIST] Re: A question about clock EMC

["Kihong Joshua Kim" <joshuakh@xxxxxxxxx>]

Han,
The extra cap reduces your rising edges which will reduce your EMI contents
as well described in your e-mail.

Regarding signal integrity, it is very likely to loose rectangular signal
shape if you add the extra cap.
But since your clock signal has very narrow bandwidth even with spread
scheme, you do not have many things (frequency domain components) to lose in
terms of signal integrity.
Signal integrity has more meaning when you are dealing with broadband
signals. (i.e. Random binary NRZ sequency in electronic SI world, mostly)

However, since you are dealing with critical CLOCK signal, you might want to
consult on its intrinsic jitter and some additional clock delay due to
this extra cap. Sometimes clock buffers are actively use this scheme so that
clock can be delayed to insure the setup time margin in order for
the signals to be latched properly at input buffers. For detailed cap values
can be generally found in the data sheet of the clock buffers or clock delay
controllers that your are dealing with.

Other than those, just challenge it. I do not see any big issues.

Happy new year, Han and SI-listers!

Kihong Joshua Kim
SI in Photonics and Electronics



On 1/1/08, Han Li <jasonleehan@xxxxxxxxx> wrote:
>
> Hi, experts.
>      I am doing a board design, on which I have a 66MHz (3.3V), and a
> 25MHz(3.3) oscillator. I used seriese termination for these clock lines.
> topoloy like this
> [A]--[seriesRes]----------long line-------------[Load]
> [A] is clock source,  then resistor , then transmission line ,then load at
> end.
> But our EMC consultant recommended me to add a cap between series Resi and
> GND. The cap and resistor  are located very close. so topoloy now like
> this:
> [A]----[seriesRes]----------long line-------------[Load]
>                            |
>                          ----
>                          ----  ( capacitor)
>                            |
>                         GND
> He didnot recommentd cap's value, only  said it  may help EMC  test.
> I understand that such a cap can increase clock rising time and reduce
> frequency spectra. BUT, donnot we creat a matched transmission line using
> series resistor? Why intentionally add a cap to destroy such a matched
> line?
> Can I really get a good EMC result?
> Could anyone provide a deeped and more detailed explanation on this?
> Thank  you very much.
>
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• References:
  • [SI-LIST] A question about clock EMC
    • From: Han Li

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[SI-LIST] A question about clock EMC

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[SI-LIST] Re: A question about clock EMC

[SI-LIST] Re: A question about clock EMC