Hi, experts.
I am doing a board design, on which I have a 66MHz (3.3V), and a
25MHz(3.3) oscillator. I used seriese termination for these clock lines.
topoloy like this
[A]--[seriesRes]----------long line-------------[Load]
[A] is clock source, then resistor , then transmission line ,then load at
end.
But our EMC consultant recommended me to add a cap between series Resi and
GND. The cap and resistor are located very close. so topoloy now like this:
[A]----[seriesRes]----------long line-------------[Load]
|
----
---- ( capacitor)
|
GND
He didnot recommentd cap's value, only said it may help EMC test.
I understand that such a cap can increase clock rising time and reduce
frequency spectra. BUT, donnot we creat a matched transmission line using
series resistor? Why intentionally add a cap to destroy such a matched line?
Can I really get a good EMC result?
Could anyone provide a deeped and more detailed explanation on this?
Thank you very much.
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