FreeLists / si-list / [SI-LIST] Re: DDR Clock & Length Matching

[Jory McKinley <jory_mckinley@xxxxxxxxx>]

Hello Kenny,
More than likely you should be looking at matching electrical length between 
the add/ctrl and the clock as opposed to the physical length.  You would need 
to consider the complete path (2) below in simulations.
-Jory
Kenny Frohlich <kenny_frohlich@xxxxxxxxx> wrote: Hi All,
  I'm working on a design based on PowerPC PPC440EPx with DDR2.  The DDR2 bus 
consists of four onboard SDRAMs, but the PPC440EPx has only one DDR clock so I 
have to use a clock buffer to provide four DDR clocks to four SDRAMs (PPC440EPx 
--> Clock Buffer --> SDRAMs).  For memory bus, I have to match the length of 
Addr/Control lines to the clock.  My question is what is the length of the 
clock that I need to match?
   
  1) The length from the clock buffer to SDRAM
  or 
  2) The total length: from PPC440EPx to clock buffer + from clock buffer to 
SDRAM.
   
  Thanks,
  Kenny
   
   
 
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