FreeLists / si-list / [SI-LIST] Re: Hyperlynx vs. Signal Explorer

["Chris Cheng" <Chris.Cheng@xxxxxxxxxxxx>]

No, I am serious. I want to know.

You are telling me you have no parrallism rules nor termination scheme =
nor topology constrain on these buses and have a free for all and use =
the post route analysis to tell yourself whether it work or not ? Your =
precious DDR2 nibbles and strobes are not grouped routed switched turned =
in the same way and are randomly free running ?

Pwr integrity, that's another interesting subject. What exactly are you =
suppose to do in your post route analysis to verify those coupling and =
impedance profile issue you are talking about ? "Pkg design", what =
exactly are you packaging designing with your post route PCB ? Pick up =
every single net in your PCB memory bus and extract your package also =
and simulate the entire bus switching at the same time to verified it =
works ? I know many ways to do that without doing the above. BTW, are =
you doing the above or you are just talking about it. Talk is cheap, do =
you practice what you preach ?

What exactly are you supposed to do with coupling and impedance profile =
issue on the DIMM, do you even get a PCB model from your vendor ? Once =
again, talk is cheap, tell me what you are doing yourself, not what you =
heard from a conference or read from a paper.

"1+GHz serial links also need loss & ISI estimates for certain
cases."=20
Ok, if you have already constrain your length, via and parallelism rules =
pre-route, what is left to verify if the rules are met and there is no =
DRC ? Turn the table around, if you don't constrain the length,via and =
parallelism before hand, are you using your post-route simulation to =
assure it works ?

-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of agathon
Sent: Wednesday, January 10, 2007 5:54 PM
To: si-list
Subject: [SI-LIST] Re: Hyperlynx vs. Signal Explorer


Chris,
heh heh,  yer funny...

Good point.  I think you know the answer:
Basic timing & such is assumed ok.  What's sim'd is crosstalk effect =
where
you're pushing things, termination placement, excessive vias (1st one is =
the
worst, though), proper termination scheme vs. topology (such as the =
various
ddr2 options... not necessarily a simple choice if not a dimm), pwr
integrity (PI) for dimm stuff - esp. if there's pkg design.    =
Concerning
the PI, there really are coupling and impedance profile issues at =
ddr2-667
on a dimm.  1+GHz serial links also need loss & ISI estimates for =
certain
cases.


On 1/10/07, Chris Cheng <Chris.Cheng@xxxxxxxxxxxx> wrote:
>
> Sorry for being simple minded.
> In this day of source synchronous and serial buses.=3D20
> What exactly is needed to simulate on your PCB once the match length =
and =3D
> parallelism rules are constrained in your router and no DCR is shown.
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx
> [mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Beal, Weston
> Sent: Wednesday, January 10, 2007 2:31 PM
> To: si-list
> Subject: [SI-LIST] Re: Hyperlynx vs. Signal Explorer
>
>
>
> This discussion comes up at least once a year and the answer is still
> the same. The best description I've seen was a couple of years ago. =
All
> EDA tools suck if you use them long enough. The deeper you get into =
it,
> the more bugs you find. Don't go too deep into it and you'll be happy =
in
> your ignorance :)X=3D3D20
>
> Now, the useful answer is that you need to look at features beyond
> functions. Every SI simulator simulates digital nets to some useful
> accuracy. Does it interface well to your PCB layout tool? Do you need =
it
> to? Does it output results in the way you want to use it? Does it
> support models of the effects that you are concerned with? Does it =
have
> the post-processing (waveform measurement) that you need? Is the cost
> within your budget? Can you, and do you want to, automate the tool for
> your work flow?
>
> So before you go looking too far for the right tool, you should figure
> out what is the job you need to do. If you just want to simulate a net
> once in a while to show pretty waveforms to your manager then get the
> cheapest tool you can find that makes pretty waveforms and you both =
will
> be happy for the immediate future. If you want a fully extensible,
> highly accurate, feature rich SI tool then get ready to spend some big
> money and time to get it set up in your environment. Thereafter you =
will
> find long-term joy. Most users want something in between. That's why
> there are so many SI tools on the market. Decide what is important to
> you and then the choice of tool will be fairly obvious.
>
> Regards,
> Weston
>
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx =
[mailto:si-list-bounce@xxxxxxxxxxxxx]
> On Behalf Of agathon
> Sent: Wednesday, January 10, 2007 12:41 PM
> To: si-list
> Subject: [SI-LIST] Re: Hyperlynx vs Signal Explorer
>
> I recently received a comment about just this from an acquaintance:
> ----
> "Short answer:  anyone trying to make full use of Cadence pcb si tools
> for
> interconnect sim and who, nevertheless, recommends it could make good
> use of
> counseling of some kind... or the receivers of that info could make =
good
> use
> of a polygraph test on the one recommending.   All this based on 1st
> hand
> experience over time."
>
> ----
> No info on Hyperlynx.
>
>
>
> On 1/9/07, cdomeny <craig.domeny@xxxxxxxx> wrote:
> >
> > We are considering adding a base-model (<GHz) SI tool to our PCB
> design
> > flow and have looked at Mentor Hyperlynx EXT and Cadence Orcad Sig
> > Explorer. In research, it seems the Cadence tool does not actually
> > perform "physical extraction", but is able to do a post-layout
> analysis
> > somehow. Can anyone help?
> >
> > Hyperlynx "seems" more mature, but cost ~2X. However, we are =
concerned
> > also about post-layout, and if Hyperlynx actually extracts the =
layout,
> > it seems like a more robust method.
> >
> > Any help, insight, or guidance is appreciated.
> >
> > Thanks, - Craig
> >
> > ------------------------------------------------------------------
> >
> >
>
>
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