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[SI-LIST] Re: PCB layer stackup
- From: "Lee Ritchey" <leeritchey@xxxxxxxxxxxxx>
- To: "Doug Smith" <doug@xxxxxxxxxx>, si-list@xxxxxxxxxxxxx
- Date: Tue, 9 Jan 2007 12:53:17 -0800
Aren't we beating this topic a little hard?
> [Original Message]
> From: Doug Smith <doug@xxxxxxxxxx>
> To: <si-list@xxxxxxxxxxxxx>
> Cc: <leeritchey@xxxxxxxxxxxxx>; ChandraKanth Gajawada
<chandrakanth.gajawada@xxxxxxxxx>
> Date: 1/9/2007 11:24:04 AM
> Subject: [SI-LIST] Re: PCB layer stackup
>
> Hi Lee and the group,
>
> Isn't it more complicated that that? In the plane:
>
> If the spacing of the diff pairs is somewhat wider than the distance
> to the plane (conservative assumption to make the point) and I take
> the current right under one of the diff wires, I will see the current
> from the above trace returning on the plane. Same thing happens on the
> other wire. Just like Lee says.
>
> But, the net current in the plane is still the common mode component
> of the diff signal if I look at a width of the plane somewhat wider
> than the pair spacing.
>
> If the diff pair spacing is much closer than the plane (I don't think
> this is very common but a good thought experiment) then the
> differential plane current will be reduced under each trace and mutual
> inductance between the two diff traces will cause them to carry more
> of the other's return current.
>
> In reality, the two cases above get muddled and some fraction (may be
> small) of the return current may flow on the other diff trace and some
> (maybe most in many cases) will be in the plane.
>
> For any specific case, it would be easy to calculate, simulate, or
> build a scale model (like Howard Johnson does) and measure the currents.
>
> Doug
>
> Lee Ritchey wrote:
>
> > The return current for one member of a diff pair is not flowing in the
> > other wire. It is flowing in the planes over which it travels. Doesn't
> > matter what the name of the planes are. EM fields have not been taught
how
> > to read yet, so they don't know what you named the planes and don't
care!
> >
> >
> >
> >>[Original Message]
> >>From: ChandraKanth Gajawada <chandrakanth.gajawada@xxxxxxxxx>
> >>To: <si-list@xxxxxxxxxxxxx>
> >>Date: 1/9/2007 8:47:52 AM
> >>Subject: [SI-LIST] Re: PCB layer stackup
> >>
> >>Hi All,
> >>One basic Doubt,(May not be related to this Subject)
> >>
> >>Do LVDS signals needs to refer GND plane (A plane in Specific!)
> >>As differential pair has the other trace as return current,I dont think
> >>they need for a Continous plane underneath it for reference....
> >>
> >>Am I true with this Idea,Please clear?
> >>
> >>Regards
> >>Chandra kanth
> >>
> >>
> >>On 1/9/07, Curt McNamara <CurtM@xxxxxxxxxxx> wrote:
> >>
> >>>I like stack-up 2 with the suggestion of turning one of the internal
> >>>power planes to a ground plane. Here is why:
> >>>
> >>>Many times you will get lower emissions from a product by routing your
> >>>clock traces on the outer layers (assuming they are over a ground
> >>>plane). I first saw this in an IEEE EMC conference paper and experience
> >>>bears it out.=20
> >>>
> >>>The second reason is that your devices (also sources of noise) are
> >>>mounted on the outside of the board. In stack-up 2, this means they are
> >>>directly over the ground layer, also increasing coupling to ground.
> >>>
> >>>So from an EMC perspective stack-up two (with an internal ground layer
> >>>next to the power layer) is best.
> >>>
> >>> Curt=20
> >>>
> >>>Curt McNamara // senior electrical engineer=20
> >>>Logic Product Development
> >>>411 Washington Ave. N. Suite 400=20
> >>>Minneapolis, MN 55401
> >>>T // 612.436.5178
> >>>F // 612.672.9489=20
> >>>www.logicpd.com
> >>>/ / / / / / / / / / / / / / / / / / / / / / / / /
> >>>This message (including any attachments) contains confidential
> >>>information intended for a specific individual and purpose, and is
> >>>protected by law. If you are not the intended recipient, you should
> >>>delete this message and are hereby notified that any disclosure,
> >>>copying, or distribution of this message, or the taking of any action
> >>>based on it, is strictly prohibited.
> >>>
> >>>
> >>>
> >>>-----Original Message-----
> >>>From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]
> >>>On Behalf Of Kindt, Jan
> >>>Sent: Tuesday, January 09, 2007 6:26 AM
> >>>To: si-list@xxxxxxxxxxxxx
> >>>Subject: [SI-LIST] PCB layer stackup
> >>>
> >>>
> >>>Hi,
> >>>=20
> >>>I need to specify a 8layer board. Fastest edges on the board are on the
> >>>600Mbit LVDS channels : about 500ps. I have two stackups in mind :
> >>>=20
> >>> stackup 1 stackup 2
> >>>---------------------------------------------------------
> >>>L1 routing routing
> >>>Substrate
> >>>L2 power plane GND
> >>>Substrate
> >>>L3 power plane routing
> >>>Substrate
> >>>L4 GND power plane
> >>>Substrate
> >>>L5 routing power plane
> >>>Substrate
> >>>L6 routing routing
> >>>Substrate
> >>>L7 GND GND
> >>>Substrate
> >>>L8 routing routing
> >>>=20
> >>>Stackup 1 has the advantage that all routing on L5, L6 and L8 is
> >>>referenced to GND. We need to push the LVDS channels over a board to
> >>>board connector. On the board to board connector, there are GND's
> >>>between separate pairs. So we keep the same reference to GND over the
> >>>connector.
> >>>=20
> >>>Stackup 2 is the stackup I would normally use due to it's symmetry.
> >>>Signals on L3 and L6 are referenced to both GND and a power plane. But
I
> >>>don't know why I would need to favour stackup 2 over stackup 1.
> >>>=20
> >>>Can you comment om which stackup is most preferred ? Or what are the
> >>>drawbacks/advantages of one stackup to another.
> >>>=20
> >>>best regards,
> >>>Jan
> >>>
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> --
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