Date Index for si-list, 01-2007

[si-list] || [01-2007 Date Index] [01-2007 Thread Index]

[SI-LIST] Re: DDR2 Clock and DQS Lines - Moran, Brian P
[SI-LIST] Re: DDR2 Clock and DQS Lines - agathon
[SI-LIST] Re: DDR2 Clock and DQS Lines - agathon
[SI-LIST] Re: DDR2 Clock and DQS Lines - Peterson, James F \(EHCOE\)
[SI-LIST] New Opening for SI Engineer - Ed Linke
[SI-LIST] Position at Intel - Virendra
[SI-LIST] Shielding clock traces on PCB's - Coombs, William B. \(US SSA\)
[SI-LIST] Re: Shielding clock traces on PCB's - Christopher McGrath
[SI-LIST] Re: Shielding clock traces on PCB's - Salman Jiva
[SI-LIST] Severe EMI and Differential Measurements - Doug Smith
[SI-LIST] Re: Shielding clock traces on PCB's - Lee Ritchey
[SI-LIST] Re: Shielding clock traces on PCB's - Dennis Han
[SI-LIST] Re: Stimulus for spice-to-IBIS - tao xu
[SI-LIST] package- Dim - sunil bharadwaz
[SI-LIST] new web/podcast posted on small signal measurements in high EMI environments - Doug Smith
[SI-LIST] A book endorsement from Bob Ross - Roy Leventhal
[SI-LIST] Join the Anatrim revolution - Kory Lilly
[SI-LIST] A Common Design Rule Violation - Doug Smith
[SI-LIST] [Fwd: Symantec Mail Security detected prohibited content in a message sent from your address (SYM:42320213041982824699)] - Doug Smith
[SI-LIST] Stimulus Patterns - npatel
[SI-LIST] Re: Stimulus Patterns - Scott McMorrow
[SI-LIST] Ethernet simulation question - Michael Kotson
[SI-LIST] Re: [Fwd: Symantec Mail Security detected prohibited content in a message sent from your address (SYM:42320213041982824699)] - Andrew W. Riley III
[SI-LIST] OT: test - Andrew W. Riley III
[SI-LIST] Re: OT: test 2 - Andrew W. Riley III
[SI-LIST] 回复： Re: Stimulus Patterns - 靖 李
[SI-LIST] Re: Shielding clock traces on PCB's - Andrew Ingraham
[SI-LIST] Finding That Glitch (in your design) - Doug Smith
[SI-LIST] Re: Shielding clock traces on PCB's - Doug Smith
[SI-LIST] Re: Ethernet simulation question - Fabrizio . Zanella
[SI-LIST] Re: Shielding clock traces on PCB's - Lee Ritchey
[SI-LIST] Re: Shielding clock traces on PCB's - Lee Ritchey
[SI-LIST] Re: Shielding clock traces on PCB's - Kim Helliwell
[SI-LIST] Re: Shielding clock traces on PCB's - Grasso, Charles
[SI-LIST] Re: Shielding clock traces on PCB's - Doug Smith
[SI-LIST] Re: Ethernet simulation question - agathon
[SI-LIST] Re: Shielding clock traces on PCB's - Doug Smith
[SI-LIST] PCB layer stackup - Kindt, Jan
[SI-LIST] Re: PCB layer stackup - Stuart Brorson
[SI-LIST] Re: PCB layer stackup - Symon
[SI-LIST] FW: PCB layer stackup - Haldor Husby
[SI-LIST] Re: PCB layer stackup - Ed Linke
[SI-LIST] Re: PCB layer stackup - Zabinski, Patrick
[SI-LIST] Re: PCB layer stackup - Curt McNamara
[SI-LIST] Re: PCB layer stackup - Antonio . Ciccomancini
[SI-LIST] Re: PCB layer stackup - ChandraKanth Gajawada
[SI-LIST] Re: PCB layer stackup - Lee Ritchey
[SI-LIST] Re: PCB layer stackup - Zabinski, Patrick
[SI-LIST] Re: PCB layer stackup - Doug Smith
[SI-LIST] Re: PCB layer stackup - Lee Ritchey
[SI-LIST] Hyperlynx vs Signal Explorer - cdomeny
[SI-LIST] Re: PCB layer stackup - Jack Olson
[SI-LIST] Re: Ethernet simulation question - Bob Patel
[SI-LIST] Re: PCB layer stackup - ChandraKanth Gajawada
[SI-LIST] Re: PCB layer stackup - Cortex.Chen
[SI-LIST] Re: Hyperlynx vs Signal Explorer - Varun Khurana
[SI-LIST] Guard traces and Coupled bonding conductors (as promised) - Doug Smith
[SI-LIST] Re: Guard traces and Coupled bonding conductors (as promised) - Mike Monett
[SI-LIST] Re: 回复： Re: Stimulus Patterns - agathon
[SI-LIST] Re: 回复： Re: Stimulus Patterns - agathon
[SI-LIST] Re: Hyperlynx vs Signal Explorer - agathon
[SI-LIST] Re: Hyperlynx vs Signal Explorer - Scott McMorrow
[SI-LIST] Re: Hyperlynx vs Signal Explorer - Carlos Moll
[SI-LIST] Re: Hyperlynx vs Signal Explorer - agathon
[SI-LIST] Re: Hyperlynx vs Signal Explorer - Shawn Nikoukary
[SI-LIST] Re: Hyperlynx vs Signal Explorer - agathon
[SI-LIST] Re: Hyperlynx vs Signal Explorer - Thompson, Gary D \(Gary\)
[SI-LIST] Re: Hyperlynx vs Signal Explorer - ryansatrom
[SI-LIST] Re: Hyperlynx vs Signal Explorer - Aubrey_Sparkman
[SI-LIST] Re: Hyperlynx vs Signal Explorer - Kai Keskinen
[SI-LIST] Re: Hyperlynx vs. Signal Explorer - Beal, Weston
[SI-LIST] Re: Hyperlynx vs. Signal Explorer - Chris Cheng
[SI-LIST] Re: Hyperlynx vs Signal Explorer - Kai Keskinen
[SI-LIST] Re: Hyperlynx vs. Signal Explorer - Dean Gonzales
[SI-LIST] Re: Hyperlynx vs. Signal Explorer - Christopher McGrath
[SI-LIST] Re: Hyperlynx vs. Signal Explorer - Chris Cheng
[SI-LIST] Re: Hyperlynx vs. Signal Explorer - agathon
[SI-LIST] Ethernet, USB 2.0 and DVI-I Compliance testing - Bashir, Shiraz \(GE Healthcare\)
[SI-LIST] Re: Hyperlynx vs. Signal Explorer - Aubrey_Sparkman
[SI-LIST] Re: Hyperlynx vs Signal Explorer - k EPD
[SI-LIST] Re: Hyperlynx vs. Signal Explorer - Roy Leventhal
[SI-LIST] Re: Hyperlynx vs. Signal Explorer - agathon
[SI-LIST] Re: Hyperlynx vs. Signal Explorer - agathon
[SI-LIST] DDR Clock & Length Matching - Kenny Frohlich
[SI-LIST] Hyperlynx vs Signal explorer - RameshK Cozerv IN HO
[SI-LIST] Re: Hyperlynx vs. Signal Explorer - Chris Cheng
[SI-LIST] Re: Hyperlynx vs. Signal Explorer - Chris Cheng
[SI-LIST] Re: DDR Clock & Length Matching - Moran, Brian P
[SI-LIST] Re: DDR Clock & Length Matching - Jory McKinley
[SI-LIST] 答复: Re: DDR Clock & Length Matching - wang . zhenfeng
[SI-LIST] Re: Ethernet, USB 2.0 and DVI-I Compliance testing - Clewell, Craig
[SI-LIST] TEST - Edi Fraiman
[SI-LIST] Re: Shielding clock traces on PCB's - JaMi Smith
[SI-LIST] Re: Shielding clock traces on PCB's - JaMi Smith
[SI-LIST] Re: Shielding clock traces on PCB's - JaMi Smith
[SI-LIST] Re: Hyperlynx vs. Signal Explorer - agathon
[SI-LIST] Re: DDR Clock & Length Matchin - agathon
[SI-LIST] Re: Hyperlynx vs. Signal Explorer - Peterson, James F \(EHCOE\)
[SI-LIST] Re: Hyperlynx vs Signal Explorer - agathon
[SI-LIST] Re: Hyperlynx vs. Signal Explorer - ryansatrom
[SI-LIST] Re: Hyperlynx vs. Signal Explorer - Scott McMorrow
[SI-LIST] Re: Hyperlynx vs Signal Explorer - Kai Keskinen
[SI-LIST] Re: Hyperlynx vs Signal Explorer - Brahim Koudssi
[SI-LIST] Re: Hyperlynx vs. Signal Explorer - Chris Cheng
[SI-LIST] Re: Hyperlynx vs. Signal Explorer - Chris Cheng
[SI-LIST] Re: Hyperlynx vs. Signal Explorer - Todd Westerhoff
[SI-LIST] Re: Hyperlynx vs. Signal Explorer - Ken Cantrell
[SI-LIST] Re: Hyperlynx vs. Signal Explorer - Chris Cheng
[SI-LIST] Re: Hyperlynx vs. Signal Explorer - Dempsher, Ned @ CSE
[SI-LIST] HSPICE w/ Verilog-AMS model of DC/DC converter (Time Domain) - Simba Julian
[SI-LIST] Re: Hyperlynx vs. Signal Explorer - Ken Willis
[SI-LIST] Re: Hyperlynx vs. Signal Explorer - Scott McMorrow
[SI-LIST] Re: Hyperlynx vs. Signal Explorer - Aubrey_Sparkman
[SI-LIST] Re: Hyperlynx vs. Signal Explorer - Todd Westerhoff
[SI-LIST] Internal package aggressors/PCB routing - Jerry Martinson
[SI-LIST] Re: Internal package aggressors/PCB routing - Ray Anderson
[SI-LIST] Re: HSPICE w/ Verilog-AMS model of DC/DC converter (Time Domain) - Muranyi, Arpad
[SI-LIST] Re: Hyperlynx vs. Signal Explorer - Chris Cheng
[SI-LIST] Re: Internal package aggressors/PCB routing - Abe (Abbas) Riazi
[SI-LIST] Re: Internal package aggressors/PCB routing - Chris Cheng
[SI-LIST] Re: Hyperlynx vs. Signal Explorer - Dempsher, Ned @ CSE
[SI-LIST] Re: Internal package aggressors/PCB routing - Ray Anderson
[SI-LIST] Re: Internal package aggressors/PCB routing - Ray Anderson
[SI-LIST] Re: Internal package aggressors/PCB routing - Mark Alexander
[SI-LIST] Re: Internal package aggressors/PCB routing - Mark Alexander
[SI-LIST] Re: Internal package aggressors/PCB routing - Henry J. Campbell
[SI-LIST] Re: Hyperlynx vs. Signal Explorer - Scott McMorrow
[SI-LIST] Re: Hyperlynx vs. Signal Explorer - Chris Cheng
[SI-LIST] Re: Hyperlynx vs. Signal Explorer - Kai Keskinen
[SI-LIST] Re: Hyperlynx vs. Signal Explorer - Peterson, James F \(EHCOE\)
[SI-LIST] Re: HSPICE w/ Verilog-AMS model of DC/DC converter (Time Domain), DesignCon material posted - Istvan Novak
[SI-LIST] Re: Low-Q Controlled-ESR Bypass Capacitors - Istvan Novak
[SI-LIST] Advanced high spped prop question - Chris Chalmers
[SI-LIST] FW: Advanced high spped prop question - Stephen Greenhalgh
[SI-LIST] 4 Port VNA recommendations? - pritchard_jason
[SI-LIST] Meet your fellow SI-listers face to face at DesignCon! - Julian Ferry
[SI-LIST] Re: Internal package aggressors/PCB routing - agathon
[SI-LIST] Question on varying the coupling ratio on a differential pair - cookeway
[SI-LIST] Re: Internal package aggressors/PCB routing - Chris Cheng
[SI-LIST] Re: Question on varying the coupling ratio on a differential pair - Muranyi, Arpad
[SI-LIST] FW: Re: Hyperlynx vs. Signal Explorer - David Lieby
[SI-LIST] Ferrite Bead Vs. Inductor - 신연숙
[SI-LIST] Re: Ferrite Bead Vs. Inductor - 신연숙
[SI-LIST] Re: Ferrite Bead Vs. Inductor - 신연숙
[SI-LIST] Re: Question on varying the coupling ratio on a differential pair - Bill Wurst
[SI-LIST] Thanks for answering my question - Wayne Cooke
[SI-LIST] Re: Ferrite Bead Vs. Inductor - Xilei Liu
[SI-LIST] Re: Internal package aggressors/PCB routing - agathon
[SI-LIST] AW: Ferrite Bead Vs. Inductor - Pommerenke, David
[SI-LIST] Interface standards - Canes Venatici
[SI-LIST] Re: Internal package aggressors/PCB routing - QU Perry
[SI-LIST] Re: Advanced high spped prop question - Andrew Ingraham
[SI-LIST] Re: Interface standards - Andrew Ingraham
[SI-LIST] Re: Ferrite Bead Vs. Inductor - Andrew Ingraham
[SI-LIST] S-parameter - Srikanth
[SI-LIST] Re: PCB layer stackup - Andrew Ingraham
[SI-LIST] Re: Internal package aggressors/PCB routing - Ray Anderson
[SI-LIST] Re: Internal package aggressors/PCB routing - Chris Cheng
[SI-LIST] Re: Internal package aggressors/PCB routing - Chris Cheng
[SI-LIST] Re: Internal package aggressors/PCB routing - Ray Anderson
[SI-LIST] Re: Internal package aggressors/PCB routing - Chris Cheng
[SI-LIST] Regarding the technical document archive for this forum - vani.chandrasekharan
[SI-LIST] Re: Internal package aggressors/PCB routing - agathon
[SI-LIST] Dust and humidity impact on the signal - OPREA Dorin
[SI-LIST] Re: Question on varying the coupling ratio on a differential pair - Loyer, Jeff
[SI-LIST] Re: Question on varying the coupling ratio on a differential pair - Hassan O. Ali
[SI-LIST] R: Dust and humidity impact on the signal - gianguida
[SI-LIST] R: Re: Question on varying the coupling ratio on a differential pair - gianguida
[SI-LIST] Small DC resistance measurments - codymiller
[SI-LIST] Re: Question on varying the coupling ratio on a dif ferential pair - Clewell, Craig
[SI-LIST] Re: Small DC resistance measurments - Christopher.Jakubiec
[SI-LIST] Re: Dust and humidity impact on the signal - Fabrizio . Zanella
[SI-LIST] Re: Question on varying the coupling ratio on a differential pair - ryansatrom
[SI-LIST] Re: Small DC resistance measurments - Joel Brown
[SI-LIST] Re: R: Re: Question on varying the coupling ratio on a differential pair - Lee Ritchey
[SI-LIST] Re: Regarding the technical document archive for this forum - Ray Anderson
[SI-LIST] Re: Small DC resistance measurments - Lee Ritchey
[SI-LIST] Re: Internal package aggressors/PCB routing - QU Perry
[SI-LIST] Re: Question on varying the coupling ratio on a differential pair - Doug
[SI-LIST] Re: Small DC resistance measurments - Derek Walton
[SI-LIST] Re: Dust and humidity impact on the signal - Scott McMorrow
[SI-LIST] Re: R: Re: Question on varying the coupling ratio on a differential pair - OPREA Dorin
[SI-LIST] R: Re: Question on varying the coupling ratio on a differential pair - ryansatrom
[SI-LIST] Re: Question on varying the coupling ratio on a differential pair - Ihsan Erdin
[SI-LIST] Re: Dust and humidity impact on the signal - Muranyi, Arpad
[SI-LIST] Re: Dust and humidity impact on the signal - Loyer, Jeff
[SI-LIST] Re: Dust and humidity impact on the signal - Chris Padilla \(cpad\)
[SI-LIST] Re: Regarding the technical document archive for this forum - Ray Anderson
[SI-LIST] Re: Sub .100 ohm measurements - John Barnes
[SI-LIST] Re: Dust and humidity impact on the signal - Alan Hilton-Nickel
[SI-LIST] Re: R: Re: Question on varying the coupling ratio on a differential pair - johndp
[SI-LIST] Re: Regarding the technical document archive for this forum - Ivor Bowden
[SI-LIST] Re: Dust and humidity impact on the signal - Tom Biggs
[SI-LIST] Re: Question on varying the coupling ratio on a differential pair - steven.d.corey
[SI-LIST] Re: Dust and humidity impact on the signal - OPREA Dorin
[SI-LIST] Re: Internal package aggressors/PCB routing - Chris Cheng
[SI-LIST] Re: Dust and humidity impact on the signal - Grossman, Brett
[SI-LIST] Let's talk laminate induced skew - Bill Dempsey
[SI-LIST] SSTL_2 - Canes Venatici
[SI-LIST] SSTL doubts - Canes Venatici
[SI-LIST] Re: Let's talk laminate induced skew - Loyer, Jeff
[SI-LIST] Re: Let's talk laminate induced skew - Aubrey_Sparkman
[SI-LIST] Re: Let's talk laminate induced skew - Lee Ritchey
[SI-LIST] Re: R: Re: Question on varying the coupling ratio on a differential pair - Lee Ritchey
[SI-LIST] Re: R: Re: Question on varying the coupling ratio on a differential pair - Ihsan Erdin
[SI-LIST] Re: R: Re: Question on varying the coupling ratio on a differential pair - OPREA Dorin
[SI-LIST] Re: R: Re: Question on varying the coupling ratio on a differential pair - Scott McMorrow
[SI-LIST] Re: R: Re: Question on varying the coupling ratio on a differential pair - Scott McMorrow
[SI-LIST] Re: R: Re: Question on varying the coupling ratio on a differential pair - OPREA Dorin
[SI-LIST] Re: R: Re: Question on varying the coupling ratio on a differential pair - George Dudnikov
[SI-LIST] Re: S-parameter - Kinger Cai
[SI-LIST] Re: R: Re: Question on varying the coupling ratio on a differential pair - Lee Ritchey
[SI-LIST] need to find a commercial Near-field Scan service in bay area - Jane Wang
[SI-LIST] Does anyone know how to convert IBIS version 3.2 to version 1.1? - Linda Zhang
[SI-LIST] Re: Does anyone know how to convert IBIS version 3.2 to version 1.1? - Mirmak, Michael
[SI-LIST] Re: Does anyone know how to convert IBIS version 3.2 to version 1.1? - Lynne D. Green
[SI-LIST] Re: Let's talk laminate induced skew - Bob Patel
[SI-LIST] IBIS creation - Madhusudhan Kulkarni
[SI-LIST] Re: IBIS creation - Tom Dagostino
[SI-LIST] Re: IBIS creation - Henrik Madsen
[SI-LIST] Re: IBIS creation - Madhusudhan Kulkarni
[SI-LIST] Re: IBIS creation - Tom Dagostino
[SI-LIST] Re: IBIS creation - PR, Unnikrishnan
[SI-LIST] Re: R: Re: Question on varying the coupling ratio on a differential pair - OPREA Dorin
[SI-LIST] Re: Does anyone know how to convert IBIS version 3.2 to version 1.1? - Linda Zhang
[SI-LIST] How much plane under traces is required for providing return current path - Erin . McPhalen
[SI-LIST] Re: How much plane under traces is required for providing return current path - syedmhusain
[SI-LIST] Re: How much plane under traces is required for providing return current path - syedmhusain
[SI-LIST] Spice-related Application Engineer Position in San Jose - Dave Aiken
[SI-LIST] PCB Trace impedance algorithms - Sam Sam
[SI-LIST] Re: PCB Trace impedance algorithms - Patrick Jabbaz
[SI-LIST] Re: PCB Trace impedance algorithms - David Instone
[SI-LIST] Re: PCB Trace impedance algorithms - johndp
[SI-LIST] Re: PCB Trace impedance algorithms - Dodd, Ian
[SI-LIST] mEEt and gEEk SI-lister meeting reservation deadline is tomorrow! - Julian Ferry
[SI-LIST] Re: need to find a commercial Near-field Scan service in bay area - MikonCons
[SI-LIST] QLogic ISP2100 - David G Haedge
[SI-LIST] Re: Does anyone know how to convert IBIS version 3.2 to version 1.1? - Mirmak, Michael
[SI-LIST] Re: PCB Trace impedance algorithms - Sam Sam
[SI-LIST] Signal Integrity opening at LSI Logic - Matta, Kusuma
[SI-LIST] Re: QLogic ISP2100 - Fabrizio . Zanella
[SI-LIST] Re: Internal package aggressors/PCB routing - agathon
[SI-LIST] Re: Internal package aggressors/PCB routing - agathon
[SI-LIST] DDR2 - termination of UQDS - Peter Müller
[SI-LIST] 4 Port VNA recommendations? - pritchard_jason
[SI-LIST] BGA Current - Madhusudhan Kulkarni
[SI-LIST] Re: BGA Current - ganeshkumar.m
[SI-LIST] PCI Express Edge Connector Models - Gregory R Edlund
[SI-LIST] Re: BGA Current - Aubrey_Sparkman
[SI-LIST] Re: BGA Current - Richard P EVANS
[SI-LIST] Re: BGA Current - Clewell, Craig
[SI-LIST] Re: 4 Port VNA recommendations? - Grossman, Brett
[SI-LIST] Agenda, IBIS Summit at DesignCon for Feb. 1, 2007 - Mirmak, Michael
[SI-LIST] Re: Internal package aggressors/PCB routing - Chris Cheng
[SI-LIST] Re: Question on varying the coupling ratio on a differential pair - dgun
[SI-LIST] Re: PCB Trace impedance algorithms - dgun
[SI-LIST] Re: 4 Port VNA recommendations? - Barnes, Heidi