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Thread Index for si-list, 01-2006

[si-list] || [01-2006 Date Index] [01-2006 Thread Index]

  1. [SI-LIST] Test PCB structures, Jim Antonellis
  2. [SI-LIST] Re: Test PCB structures, Zabinski, Patrick J.
  3. [SI-LIST] Re: PCI-X 1.0a simulation, Sanchayan Sinha
  4. [SI-LIST] SI Jobs in Austin, TX, Brent Rogers
  5. [SI-LIST] SI Contract With Intel in Chandler, AZ, James Van
  6. [SI-LIST] IBIS modelling in PSpice, nrpatel
  7. [SI-LIST] Re: IBIS modelling in PSpice, Muranyi, Arpad
  8. [SI-LIST] how to model frequency dependent resistor using hspice?, Wang Dustin
  9. [SI-LIST] Connector impedance mismatch, danielesperante1
  10. [SI-LIST] differential pairs on backplane connectors, Stephen Greenhalgh
  11. [SI-LIST] European IBIS Summit At DATe 2006 - Second Call for Paper/Call for Participation, Ralf Bruening
  12. [SI-LIST] FW: IBIS modelling in PSpice, Chris Schmolze
  13. [SI-LIST] Re: XAUI, Brian Von Herzen
  14. [SI-LIST] Re: Paksi-E Model Dielectric Constants, Ken Willis
  15. [SI-LIST] METASTABILITY, Somesh Dhavala
  16. [SI-LIST] Re: FW: IBIS modelling in PSpice, Muranyi, Arpad
  17. [SI-LIST] Re: METASTABILITY, Muranyi, Arpad
  18. [SI-LIST] Re: differential pairs on backplane connectors, Julian Ferry
  19. [SI-LIST] small changes, big effects, Doug Smith
  20. [SI-LIST] FW: Re: FW: IBIS modelling in PSpice, Chris Schmolze
  21. [SI-LIST] Maximum frequency consideration for high-speed digital analysis o f differential signals, rula . bakleh
  22. [SI-LIST] Re: Maximum frequency consideration for high-speed digital analysis of differential signals, art_porter
  23. [SI-LIST] Re: si-list Digest V6 #4, Daniel Jones
  24. [SI-LIST] IBIS in PSpice, Lynne D. Green
  25. [SI-LIST] preferred math package?, Zabinski, Patrick J.
  26. [SI-LIST] So you want to be a consultant, Doug Smith
  27. [SI-LIST] Re: Maximum frequency consideration for high-speed digital analysis of differential signals, Cortex.Chen
  28. [SI-LIST] about ibis model validation, zheng qi
  29. [SI-LIST] An si-list meeting at DesignCon 2006, Peterson, James F (FL51)
  30. [SI-LIST] SI Job posting Vancouver BC Canada PMC-Sierra, Barry Rowland
  31. [SI-LIST] Re: preferred math package? (summary), Zabinski, Patrick J.
  32. [SI-LIST] Inter Symbol Interference (ISI), Chandra Kanth
  33. [SI-LIST] Inter Symbol Interference (ISI)., Chandra Kanth
  34. [SI-LIST] Job Posting - Amphenol Corp, Sidney, NY, John Birkett
  35. [SI-LIST] Opening for experienced SI engineer in San Diego, Michalka, Tim
  36. [SI-LIST] 6 Layer microvia stackup, Andrew Seddon
  37. [SI-LIST] Update on Pulse Research Lab clock divider sample, Tang, George
  38. [SI-LIST] Re: 6 Layer microvia stackup, Dhiraj Kiran
  39. [SI-LIST] PCB Impedance Failure, Clayton Wrobel
  40. [SI-LIST] Re: PCB Impedance Failure, Clewell, Craig
  41. [SI-LIST] ASIC Pinout / Package, nrpatel
  42. [SI-LIST] unsubscribe, Allan Davidson
  43. [SI-LIST] Quick analysis of a branched nets, Fields, Brian
  44. [SI-LIST] Heat Dissipation Factor, VSelvasuganthi
  45. [SI-LIST] Part 2So You Want to be a Consultant, Doug Smith
  46. [SI-LIST] Overshoot / Undershoot, Andrew Seddon
  47. [SI-LIST] Re: OT: RoHS and Lead, Chandra Kanth
  48. [SI-LIST] SI Modeling Tutorial/Survey at PCI SIG DevCon-Europe and DesignCon 2006, Pratt, Gary
  49. [SI-LIST] Re: Overshoot / Undershoot, Ken Willis
  50. [SI-LIST] Immediate Signal Integrity Engineer Opening at Xilinx Inc. San Jose, Ray Anderson
  51. [SI-LIST] Introduction to Microelectronics Packaging course at San Jose State, Raj Raghuram
  52. [SI-LIST] Can anyone send me the BCM5466SR IBIS model, Peter Zhu
  53. [SI-LIST] How to use S-parameter accurately, TerenceHsieh
  54. [SI-LIST] Engineering Influence, Doug Smith
  55. [SI-LIST] SPI 2006 - Call for Papers, Andre Grabinski
  56. [SI-LIST] Loop Inductance, jen guest
  57. [SI-LIST] Buffer placement, Babid A
  58. [SI-LIST] Eye diagram, Stephen Greenhalgh
  59. [SI-LIST] Re: Eye diagram, jose_moreira
  60. [SI-LIST] Reflection around threshold point, Andrew Seddon
  61. [SI-LIST] Series termination greater than the characteristic impedance?, aminotg
  62. [SI-LIST] Length of Discontinuity, Andrew Seddon
  63. [SI-LIST] Re: Length of Discontinuity, Curt McNamara
  64. [SI-LIST] Re: Series termination greater than the characteristic impedance?, Grasso, Charles
  65. [SI-LIST] Multiple SI/characterization engineer positions at Altera (San Jose, CA), Geping Liu
  66. [SI-LIST] Re: si-list Digest V6 #14, Clayton Wrobel
  67. [SI-LIST] Length matching on Gb lines, richard moffat
  68. [SI-LIST] Re: Length matching on Gb lines, richard moffat
  69. [SI-LIST] Questions concerning DC-block Caps and coaxial optical packages ( ROSA/TOSA), Bernard Harris
  70. [SI-LIST] Re: Series termination greater than the characteristic impedance?, Gilles Aminot
  71. [SI-LIST] Rest mail Please ignore, Kedar P Apte
  72. [SI-LIST] Decoupling Cap. Strategies., Kedar P Apte
  73. [SI-LIST] It's Just a Small Design Change!, Doug Smith
  74. [SI-LIST] Best device model to learn SI, john matt
  75. [SI-LIST] Re: Best device model to learn SI, Hargin, Bill
  76. [SI-LIST] SI Job Posting Optimal Corporation, Henry J. Campbell
  77. [SI-LIST] Spice measurements, Adrianna
  78. [SI-LIST] test, Aubrey_Sparkman
  79. [SI-LIST] Signal Integrity Engineer position-Intel Corporation, Chandler, AZ, Clock, StevenX A
  80. [SI-LIST] What makes a good technical course/seminar?, Doug Smith
  81. [SI-LIST] cml specifications, david stern
  82. [SI-LIST] Ethernet standards coding and data frequency, Jean_Pierre . Bouthemy
  83. [SI-LIST] differential impedance, Stephen Greenhalgh
  84. [SI-LIST] Opinions wanted on Signal Integrity analysis tools, tom_cip_11551
  85. [SI-LIST] Re: Opinions wanted on Signal Integrity analysis tools, Grasso, Charles
  86. [SI-LIST] Re: differential impedance, Dr. Edward P. Sayre
  87. [SI-LIST] SPI 2006 - Deadline Extension, Andre Grabinski
  88. [SI-LIST] Boston Area Job Opening, Bill Kofoed



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