FreeLists / si-list / [SI-LIST] Re: DDR SDRAM signal routing

["Tom Clarke" <tomtsi@xxxxxxxxxxxxxxxx>]

Pulsonix has a very good package.

Tom Clarke
Technology Sales, Inc.
Ph: 801-572-1588
www.tsi-reps.com
www.pcb-sw.com
Engineers Helping Engineers


-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Ray Anderson
Sent: Monday, January 03, 2005 9:28 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: DDR SDRAM signal routing


Klim-

How about these for a starter: Spice (Hspice, Pspice, Nspice, Smartspice 
or other variants), Eldo, Specctraquest, Hyperlynx, ADS, or other time 
domain simulator.

In short, just about any time domain simulator should be up to the task.

-Ray


Klim wrote:

>Ray Anderson,
>    Can you tell what kind tool can simulate DDR SDRAM termination 
>resister
>on PCB?
>
>Best,
>    Klim
>
>
>----- Original Message -----
>From: "Ray Anderson" <reanderson@xxxxxxxxxxxxx>
>To: <si-list@xxxxxxxxxxxxx>
>Sent: Monday, November 08, 2004 11:28 PM
>Subject: [SI-LIST] Re: DDR SDRAM signal routing
>
>
>  
>
>>Ray Anderson wrote:
>>
>>You mentioned that you don't have the "possibility to run 
>>simulations". I would submit that it is almost mandatory to simulate 
>>complex, high-speed interfaces prior to committing a design to fab if 
>>you don't want to go thru multiple iterations of the board prior to 
>>finding a topology that works well (if at all). The cost of simulating 
>>(and there are some low or no cost solutions) is much less than the 
>>costs you'll incur with the 'cut and try' approach.
>>
>>App-notes and rules of thumb will only get you pointed in the right 
>>direction, but I feel simulation is the real key to understanding what 
>>is happening in any particular design (assuming the design is modeled 
>>correctly).
>>
>>-Ray Anderson
>>
>>Senior Signal Integrity Staff Engineer
>>Xilinx Inc.
>>
>>    
>>
.
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