FreeLists / si-list / [SI-LIST] Re: problem adjustable low dropout regulator

[steve weir <weirsp@xxxxxxxxxx>]

Jan,

As Istvan noted, you likely have a stability problem.  Most of National's 
LDOs require significant ESR to function properly.  Ironically, the higher 
the load current, the higher the minimum ESR.  National stipulates ESR 
values of:

Input - ESR / Cin < 1.5milliohms / uF

Output - 0.2 ohms < ESR < 5 ohms which pretty much means a garden variety 
tantalum.  A low ESR tantalum, multiple tantalums in parallel, or a bunch 
of ceramic caps such as are probably decoupling the FPGA and bridge are 
trouble.

The other requirement on that part when used in adjustable mode is a shunt 
capacitor in the feedback of 68-100pF.

Just to add to the charm of that part, it also has some start-up issues.

I like some of National's parts but that one I find the 3964 a bit 
lacking.  You might check to see if one of Linear Tech's parts can drop in 
replace.  LT's newer LDO's do not impose ESR requirements on the output 
cap, and tend to be very well behaved.

Steve.

At 12:06 PM 1/6/2004 +0100, Jan Vercammen wrote:
>Hello si-list,
>first of all my best whishes for 2004.
>
>I need your help on a problem with an adjustable low dropout regulator or
>LDO for short.
>We have spent considerable effort on this and we are stuck. It concerns a
>National LP3964-ADJ
>800mA LDO in a SOT-223 package.
>I am not stating that this component is a bad device, only that in our
>application we are
>experiencing some unexpected problems.
>
>Let me first decribe the LDO. It is a CMOS chip with a P-MOS pass
>transitor. A resistor feedback
>divider (with one capacitor) is compared with an internal reference
>voltage of 1.215V. The circuit
>is as described in the data sheets and is very simple.
>The input voltage is 3.3V, the output voltage is 2.5V. Both voltages are
>supplied by internal planes.
>The 2.5V is suplied to the core of a Motorola MPC107 bridge and to the
>core of an Altera EP10K30
>FPGA. We have measured a 2.5V current of 230mA. These LDO circuits are
>used on several
>printed circuit boards (most PCBs are 12 layers, one is 10 layer).
>
>We have experienced two problems, they are not necessarily related, but
>likey are.
>- First problem: the 2.5V drops exponentially by about 300-400mV over
>50-100us and then ramps up
>very quickly in about 2-3us. The drop starts - we think - when the 107
>bridge and FPGA enter a low
>activity faze. The ramp - we think - starts when the bridge and FPGA
>become active again. The
>voltage drop of 400mV on the bridge and FPGA core voltage does not create
>any functional problems!
>- Second problem: there are problems with the target value of the 2.5V. On
>most boards we have
>a problem of obtaining 2.5V, we only get 2.25V to 2.4V. We also
>experimented with a setting of 2.7V, which
>we need for a future design. If we adjust the resistors for 2.8V, we only
>obtain 2.5V. We have measured the
>voltage after the resitive divider an found about 1.15V and not  - what
>you would expect - the reference
>voltage of 1.215V. It seems that the internal voltage reference has
>changed in value or that the
>internal amplifier(s) is plagued by DC offsets.
>
>Here is what we did to improve some of the problems:
>-1- a non-adjustable LDO (with internal feedback network) does not have
>the DC-offset or the voltage drops!
>-2- we used Kelvin connections for the feedback and bulk (tantalum)
>decoupling, but this does not seem to help
>-3- a 1.5Amp LDO version seems to behave somewhat better with respect to
>DC-offset and voltage drops
>-4- using 1 ohm series resistors on the tantalums  (2x22uF) helps to
>remove the voltage drops
>-5- a bleeder resistor (25-100mA) helps to remove some of the voltage
>drops
>-6- mounting the feedback circuit to the top of the PCB does not make a
>difference
>-7- using a ferrite bead in series with the input does not seem to help
>-8- the voltage drops are very sensitive to the output decoupling, but
>this depends on the ESR of the bulk (tantaal)
>       decoupling and not on the ceramic capacitors (about 12x 100nF on
>2.5V)
>-9- extra resistance and/or inductance on the output removes the voltage
>drops - e.g. a long fat track (of about 16mOhm)
>       or a power supply track grid
>-10-  a higher input voltage (of 5V) does not help
>-11- removing the FPGA from the 2.5V does not help
>
>So here are our questions:
>-1- can anyone explain why a fixed LDO (using an internal feedback
>network) does NOT have the problems
>       of a adjustable LDO. A fixed LDO does not need the measures of the
>list above - it is always OK!!
>-2- is it possible that the SOT-223 package is the problem? Has anyone
>experience in this respect? Is another
>       package better (e.g. TO-263 or TO220)??
>-3- can anyone explain the shift of the inernal voltage reference? Or are
>the internal OPamps experiencing
>       an out-of-band response of RF noise on the 3.3V or 2.5V??
>-4- Can you use an LDO with a 3.3V+/-5%  input voltage and 2.7V+/-5%
>output voltage??
>
>We are stuck here. Currently one scenario is to consider another component
>from - possibly - another
>manufacturer. But that may not be a good idea as we may end up in the same
>situation.
>
>
>Any hint or help is appreciated.
>
>Kind regards,
>
>Jan Vercammen
>
>
>
>
>
>Kind regards,
>
>Jan Vercammen
>Agfa-Gevaert NV
>Mortsel, Belgium
>
>
>
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