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[SI-LIST] Fwd: Re: Re: Bypass Capacitor Selection
- From: steve weir <weirsp@xxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Fri, 02 Jan 2004 13:16:08 -0800
>Date: Fri, 02 Jan 2004 09:18:11 -0800
>To: leeritchey@xxxxxxxxxxxxx, "David Anthony" <x2y@xxxxxxx>,
>jmartinson@xxxxxxxxxxxxxxxxx, si-list@xxxxxxxxxxxxx, si-list@xxxxxxxxxxxxx
>From: steve weir <weirsp@xxxxxxxxxx>
>Subject: Re: [SI-LIST] Re: Bypass Capacitor Selection
>
>Lee,
>
>I have become a big believer in the X2Y parts over the past several
>years. While, the land patterns naturally suit themselves to multiple
>vias to mitigate the effects of attachment inductance, the presence of the
>G1/G2 plates make these devices perform much better than anything else I
>have seen, ( as well as offering some applications regular caps can't do
>at all ). I love these things for SMPS and decoupling. The limited
>sources of supply used to make them costly and hard to get, but that has
>improved quite a bit in the past 24 months, to the point where they are
>both performance and cost effective.
>
>One of the really amazing characteristics of these devices is the very
>well behaved and lower impedance floor. Since we are limited largely by
>how many vias we attach with, these devices are about as close to ideal as
>we can get. I think it would be well worth your while to reevaluate
>decoupling to any particular target impedance using X2Ys versus any
>alternative. I believe you will be very pleasantly surprised.
>
>Steve.
>
>
>At 08:40 AM 1/2/2004 -0800, Lee Ritchey wrote:
>>This is a good subject to explore. However, focusing on the parasitic
>>inductance of the capacitor itself is too narrow a view. What counts is
>>the total inductance, including the mounting pads and vias. On multilayer
>>PCBs, the mounting inductance dominates the picture. When this had been
>>taken into account, the ultralow inductance capacitors turn out to be not
>>much better than the standard two terminal devices.
>>
>>While I haven't published any papers specifically on this topic, nor have I
>>seen anyone else do so, we did treat this topic in great detail with many
>>lab measurements in the book I published late last year. Don't mean to
>>push the book in this reply, but want to make sure the information is
>>visible to those who are curious.
>>
>>On my web site, there is a list of articles, one by Micheal Grime and one
>>by the engineers at UMR which sheds some light on the overall topic of
>>capacitor selection. site is www.speedingedge.com
>>
>>
>>Lee
>>
>>
>> > [Original Message]
>> > From: David Anthony <x2y@xxxxxxx>
>> > To: <jmartinson@xxxxxxxxxxxxxxxxx>; <si-list@xxxxxxxxxxxxx>;
>><si-list@xxxxxxxxxxxxx>
>> > Date: 12/30/2003 2:27:02 PM
>> > Subject: [SI-LIST] Re: Bypass Capacitor Selection
>> >
>> > Jerry,
>> >
>> > Here are links to comparisons of standard discretes (also reverse aspect
>> > caps) vs. an X2Y cap. The 4-terminal X2Y's internal design promotes
>> > cancellation of mutual inductance. There have been discussions on the list
>> > as to what's the best test board for comparing vendor components and we
>>look
>> > forward to a standard emerging. We choose a PCB similar to one used by UMR
>> > in a paper they presented at the 2002 EMC Symposium. Bart Bouma of
>> > Yageo/Phycomp also compared X2Y to standard discretes on a similar board.
>> >
>> > Links to data (watch for URL wrap):
>> >
>> > (1) X2Y vs.(5)different valued discretes(same size caps):
>> >
>>http://www.x2y.com/cube/x2y.nsf/(files)/X2YPCB121203.pdf/$FILE/X2YPCB121203.
>> > pdf
>> >
>> >
>> > Phycomp data: X2Y vs. standard discretes and low L reverse aspect caps
>> > (0306):
>> >
>>http://www.x2y.com/cube/x2y.nsf/(files)/092703X2YReverse.pdf/$FILE/092703X2Y
>> > Reverse.pdf
>> >
>> > regards,
>> > Dave
>> >
>> >
>> >
>> >
>> >
>> > -----Original Message-----
>> > From: si-list-bounce@xxxxxxxxxxxxx
>> > [mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Jerry Martinson
>> > Sent: Tuesday, December 30, 2003 2:18 PM
>> > To: si-list@xxxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
>> > Subject: [SI-LIST] Re: Bypass Capacitor Selection
>> >
>> >
>> > Martin,
>> >
>> > To address your 3rd question, I'm a bit of a maverick as I believe that
>> > using surface mount capacitor arrays are an often-overlooked trick for
>> > having better decoupling performance at a reasonable cost. With most
>> > designs, the via inductance is a large part of the impedance, cap
>> > inductance is also a larger but smaller component. To reduce this, it
>> > makes sense to try to cram the vias for the two voltages close together
>> > and it also makes sense to try to have more vias and caps in parallel.
>> > There are limits to how much of this you can achieve for DFM, routing,
>> > cost, and other reasons.
>> >
>> > For DFM reasons, you'll likely need to space your 0402 and 0603
>> > components further apart from each other than you'd ideally like. This
>> > will limit your cap and via density. You'll also have some DFM
>> > resistance to putting the vias as close together and as close to the SMT
>> > pads as you'd ideally like. Cap arrays can partially solve these
>> > problems. Here are some points about using the cap arrays:
>> >
>> > 1. They effectively put 4 0402 or smaller parts in the same area as an
>> > 1206 or smaller. This means you can get a higher number of caps and
>> > vias in a given area. =20
>> > 2. Interdigitate so that much of the inductance works for you instead
>> > of against you. Alternate power and ground so that the power isn't all
>> > on one side and the ground is on the other. There is a paper from AVX
>> > on using expensive IDC cap arrays that show this. I think the IDC cap
>> > arrays are nice but expensive. Using regular cap arrays on pads
>> > designed for the AVX IDC cap arrays, you can get the beneficial
>> > interdigitated mutual inductance in your vias, which are the larger part
>> > of the inductance. Another benefit of this is that if your decoupling
>> > is found to be inadequate after your boards are made, you can use these
>> > AVX IDC cap arrays without spinning your board.
>> > 3. You may not be able to have the vias for the two voltages point
>> > inward from the pads like you might have been able to with discretes.
>> > So you'll have to look at your board's DFM rules. This may be a
>> > disadvantage of using the cap arrays.
>> > 4. The purchase cost of the cap arrays is higher than 4 discretes.
>> > Average placement, etc... costs for each discrete are usually a couple
>> > US cents. These costs per discrete always exist but may not be
>> > internalized in the assembly pricing you see. You'll have to look at
>> > the economic ramifications of this. The situations I've seen slightly
>> > favor an array versus four discretes so you can actually _SAVE_ money
>> > and have better decoupling.
>> > 5. You can only use one value for the four elements in an array. This
>> > may conflict with your other decoupling goals.
>> > 6. You can't spread an array around like you can with discretes.
>> >
>> > I must caution you that I have not been able to do very good
>> > quantitative measurements comparing the cap array trick's effectiveness
>> > versus the discrete caps effectiveness in perfect apples to apples
>> > tests. However based on the differences I've seen in similar boards
>> > where I used discretes on one and arrays on another, I'm pretty sure
>> > that using cap arrays has given me substantially less noise. So using
>> > cap arrays are more art than science right now. I wish I had hard data
>> > showing how good arrays as a function of X, Y, Z compared to discretes,
>> > but I don't have the time or resources to do this personally.
>> >
>> > I'd sure be interested in hearing if anybody else has tried this or has
>> > hard data.
>> >
>> > -Jerry
>> >
>> > -----Original Message-----
>> > From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
>> > On Behalf Of SI List
>> > Sent: Tuesday, December 30, 2003 5:21 AM
>> > To: si-list@xxxxxxxxxxxxx
>> > Subject: [SI-LIST] Bypass Capacitor Selection
>> >
>> > Dear All,
>> >
>> > After studying many books, the bottom line for high frequency bypass
>> > capacitor selection seems to be the following:
>> >
>> > Use the smallest possible package and then take the largest valued
>> > capacitor available in that package.
>> >
>> > Although 0201 capacitors are available, they are kind of hard to
>> > assemble. So in our design, we are thinking of using 0402 X5R parts.
>> >
>> > In a 0402 package, the largest value available seems to be 1 uF.
>> >
>> > My frequency range of interest is DC to 500 MHz. In addition to the
>> > bypass capacitors, I know that there must be a pair of closely spaced
>> > VCC/GND reference planes.
>> >
>> > My questions:
>> > 1. Does it make sense to only use 1 uF 0402 capacitors for bypassing?
>> > Other people often use a combination of 1 nF/10nF/100nF. 2. I have been
>> > looking at the frequency characteristic of 100 nF 0402 X5R capacitors
>> > given in the data sheets of different manufacturers. The impedance vs.
>> > frequency plot often looks quite different from manufacturer to
>> > manufacturer. Should I choose the manufacturer with the best frequency
>> > characteristic or are all such parts almost equivalent? 3. Does it make
>> > sense to use surface mount capacitor arrays for bypassing?
>> >
>> > Thanks for all your expert feedback.
>> >
>> > Best regards,
>> > Martin Heimlicher, heimlicher__at__enclustra//dot//com
>> >
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>>
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