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Thread Index for si-list, 01-2003

[si-list] || [01-2003 Date Index] [01-2003 Thread Index]

  1. [SI-LIST] Happy new year!!!!!!!!!!!!!!!!, Sathish
  2. [SI-LIST] Happy New year., Inmyung Song
  3. [SI-LIST] problem about resistor on chip, Bi Han
  4. [SI-LIST] Looking for soft copy of old wl gore paper on eye diagrams....., Michael_Greim
  5. [SI-LIST] FW: Using translated EBD models in Eplanner-scratchpad - Resend, Gupta, Anurag x4500
  6. [SI-LIST] LVDS & TMDS, Ched-Chang Chai
  7. [SI-LIST] Re: LVDS & TMDS, ZL e-Studio
  8. [SI-LIST] More efffects of paths crossing ground plane breaks, Doug Smith
  9. [SI-LIST] Re: Regarding Pull down, Mike Brown
  10. [SI-LIST] about dc-offset compensation in amplifier, Bi Han
  11. [SI-LIST] How to calculate the resistance and inductance of vias, Zhangkun
  12. [SI-LIST] Re: How to calculate the resistance and inductance of vias, Ingraham, Andrew
  13. [SI-LIST] Using translated EBD models in Eplanner-scratchpad - Resend, Gupta, Anurag x4500
  14. [SI-LIST] pcmcia - typical ibis model, k EPD
  15. [SI-LIST] calculating difference impedance for broadside coupled signals, Sachin Chheda
  16. [SI-LIST] New Article and Class, Scott McMorrow
  17. [SI-LIST] Wireless board interconnect, John Coupland
  18. [SI-LIST] transmission line equations, Nick Paulter
  19. [SI-LIST] Senior Signal Integrity Engineer Position Available, Frank Yuan
  20. [SI-LIST] Package model in spectraquest, sudheer_bs
  21. [SI-LIST] Re: Package model in spectraquest, John Horner
  22. [SI-LIST] Re: Wireless board interconnect, John Coupland
  23. [SI-LIST] Mentor to XTK translation problem, Perry Qu
  24. [SI-LIST] chip inductors, C Deibele
  25. [SI-LIST] Re: Mentor to XTK translation problem, Donkle, Steve
  26. [SI-LIST] Skew boards, Hora Abu
  27. [SI-LIST] Parallel Resonance of crystall oscillator, Parthasarathy Sampath
  28. [SI-LIST] Re: chip inductors, Morgenstierne, Christian
  29. [SI-LIST] SV: Re: Mentor to XTK translation problem, Anders Ekholm (EAB)
  30. [SI-LIST] Re: SI/Timing tool survey, Peterson, James F (FL51)
  31. [SI-LIST] 10 Gbps Driver/Receiver IBIS model, Gangyao Xiao
  32. [SI-LIST] Re: How to connect vias to power ground plane?, nsi041350-Roberts
  33. [SI-LIST] Planar EM solvers?, Fasig, Jonathan L.
  34. [SI-LIST] Re: 10 Gbps Driver/Receiver IBIS model, Korcz, Cezary
  35. [SI-LIST] Re: Parallel Resonance of crystall oscillator, ViswanathanRavi
  36. [SI-LIST] Platform Conference, Beal, Weston
  37. [SI-LIST] Re: (no subject), Matthew Herndon
  38. [SI-LIST] FR4 non-linear, Loyer, Jeff
  39. [SI-LIST] Resistor Calculator, PYHTILA,JOHN (HP-Cupertino,ex1)
  40. [SI-LIST] hspice issue, Bi Han
  41. [SI-LIST] Voltage drop across the Inductance, Jayaprakash Balachandran
  42. [SI-LIST] Re: Voltage drop across the Inductance, John Spohnheimer
  43. [SI-LIST] RMCEMC January Meeting Announcement, Charles Grasso
  44. [SI-LIST] new paper posted, Doug Smith
  45. [SI-LIST] Re: hspice issue, Bi Han
  46. [SI-LIST] vias in flex circuits, Jan Vercammen
  47. [SI-LIST] Ceramic caps, Lucas Bossetti
  48. [SI-LIST] Differential Timing in IBIS, Timothy Coyle
  49. [SI-LIST] Re: (no subject) - summary, Matthew Herndon
  50. [SI-LIST] clocking using CPLD, hariharan
  51. [SI-LIST] HCSL Ibis Model, Manor, Ben
  52. [SI-LIST] SI with IBIS models for ECL devices., Paliakara, Vinod
  53. [SI-LIST] Re: clocking using CPLD, James_R_Jones
  54. [SI-LIST] Job openings at Sigrity, Teo Yatman
  55. [SI-LIST] [Fwd: Re: Differential Timing in IBIS], Robert Haller
  56. [SI-LIST] Lumped vs. Distrbuted systems., Michael Frandsen
  57. [SI-LIST] Re: Resistor Calculator, Claudio Girardi
  58. [SI-LIST] HSTL class-III, rajat . chauhan
  59. [SI-LIST] European IBIS Summit Announcement, Ross, Bob
  60. [SI-LIST] Validate your IBIS models - quickly and completely!, Lynne Green
  61. [SI-LIST] Re: Validate your IBIS models - quickly and completely!, Lynne Green
  62. [SI-LIST] Re: S-parameter use summary, MikonCons
  63. [SI-LIST] looking for IBIS models, Kevin Buchanan
  64. [SI-LIST] ground plane cut-out pattern for SMA connectors, Gregory R Edlund
  65. [SI-LIST] Re: SI with IBIS models for ECL devices., Paliakara, Vinod
  66. [SI-LIST] Re: HSTL class-III, rajat . chauhan
  67. [SI-LIST] Re: Resistor Calculator (off topic), Claudio Girardi
  68. [SI-LIST] Re: ground plane cut-out pattern for SMA connectors, Loyer, Jeff
  69. [SI-LIST] spice modeling for organic build-up substrates, Javier DeLaCruz
  70. [SI-LIST] Re: spice modeling for organic build-up substrates, Anil Pannikkat
  71. [SI-LIST] Ethernet Magnetic Jacks, Youssef Khalife
  72. [SI-LIST] Hard drive paper posted, Doug Smith
  73. [SI-LIST] DDR skew, chendla
  74. [SI-LIST] bidirectional line driver needed, Nico Fleurinck
  75. [SI-LIST] Re: bidirectional line driver needed, Ingraham, Andrew
  76. [SI-LIST] Re: New Article and Class, Vieira, Keith
  77. [SI-LIST] SI Engineer Job Opening at Stratus in Maynard, MA, Mango, Steve
  78. [SI-LIST] si-list administrivia......., Ray Anderson
  79. [SI-LIST] Flight time skew due to Dk varation, Perry Qu
  80. [SI-LIST] Re: Flight time skew due to Dk varation, Loyer, Jeff
  81. [SI-LIST] chip cap topology, Ed Priest
  82. [SI-LIST] chip cap topology - retry, Ed Priest
  83. [SI-LIST] Re: Ethernet Magnetic Jacks, Mandrusov, Vladimir
  84. [SI-LIST] Any body have gscan & tkdiff on solaris, Bi Han
  85. [SI-LIST] HELP, pcb dsd
  86. [SI-LIST] please provide me ibis model of HCPL 6651 ASAP, pcb dsd
  87. [SI-LIST] Combining DC and TRANS analysis, Shee Kian Wong
  88. [SI-LIST] RMCEMC January Meeting reminder, Grasso, Charles
  89. [SI-LIST] Re: Combining DC and TRANS analysis, Ingraham, Andrew
  90. [SI-LIST] Seminar on Embedded Passives, William M. Balliette/AT-Austin/3M/US
  91. [SI-LIST] Coplanar differential signals, Mroczkowski, Jason
  92. [SI-LIST] Re: Coplanar differential signals, Gangyao Xiao
  93. [SI-LIST] Simulationsof a connector, Michael Kurten
  94. [SI-LIST] Re: Simulationsof a connector, christopher . heard
  95. [SI-LIST] De-coupling capacitor, Pradeep Amrithraj
  96. [SI-LIST] Re: De-coupling capacitor, Pradeep Amrithraj
  97. [SI-LIST] Re: (no subject) - full summary, Matthew Herndon
  98. [SI-LIST] RMCEMC Bonus February meeting, Charles Grasso
  99. [SI-LIST] if any body know abt any seminars in india(Bangalore), mbestha
  100. [SI-LIST] Spice-models, erno.lahteenmaki
  101. [SI-LIST] Re: Spice-models, Alicia Corrales Chanca
  102. [SI-LIST] Some issues related to spiral inductor modelling., Bi Han
  103. [SI-LIST] Is-there a Mathcad model available?, Paradis, Daniel
  104. [SI-LIST] si-list still experiencing moderation problems, Ray Anderson
  105. [SI-LIST] FWD: SI Engineer Job Opening at Stratus in Maynard, MA, Ray Anderson
  106. [SI-LIST] FWD: PCD Magazine, Ray Anderson
  107. [SI-LIST] FWD: Re: Ethernet Magnetic Jacks, Ray Anderson
  108. [SI-LIST] FWD: PCB Trace Z, C, & L relationship, Ray Anderson
  109. [SI-LIST] FWD: Routing Differential PECL Signals, Ray Anderson
  110. [SI-LIST] FWD: Beylium Copper, Ray Anderson
  111. [SI-LIST] FWD: Re:_[SI-LIST]the placement of bypass/decoupling capacitors, Ray Anderson
  112. [SI-LIST] FWD: RE: Some issues related to spiral inductor modelling., Ray Anderson
  113. [SI-LIST] Re: FWD: Berylium Copper, Julian Ferry
  114. [SI-LIST] Re: Berrylium Copper, Ray Anderson
  115. [SI-LIST] Re: FWD: Beylium Copper, Clewell, Craig
  116. [SI-LIST] Re: FWD: PCB Trace Z, C, & L relationship, Larry Smith
  117. [SI-LIST] How complete waveform created?, Jack W.C. Lin
  118. [SI-LIST] help me guys, mbestha
  119. [SI-LIST] Re: Some issues related to spiral inductor modelling., Bi Han
  120. [SI-LIST] Re: FWD: RE: Some issues related to spiral inductor modelling., Swanson, Dan
  121. [SI-LIST] Re: FWD: RE: Some issues related to spiral inductor modelling., Chandrasekhar Arun
  122. [SI-LIST] Re: over & under shoots, James_R_Jones
  123. [SI-LIST] HFSS solution issue, Bi Han
  124. [SI-LIST] Re: Question on IBIS: rising/falling waveform - How complete waveform created?, Muranyi, Arpad
  125. [SI-LIST] Re: HFSS solution issue, Swanson, Dan
  126. [SI-LIST] Re: question on IBIS: rising/falling waveform., Ingraham, Andrew
  127. [SI-LIST] Model generation, Bob Patel
  128. [SI-LIST] Cosmoscope for eye-diagrams ??, Ray Anderson
  129. [SI-LIST] Re: Cosmoscope for eye-diagrams ??, Ray Anderson
  130. [SI-LIST] Stub length of a clock, Hora Abu
  131. [SI-LIST] Re: Stub length of a clock, James_R_Jones
  132. [SI-LIST] Steve Wood/TOSHIBA_TEE is out of the office., Steve . Wood
  133. [SI-LIST] Re: Question on IBIS: rising/falling waveform - H ow complete waveform created?, Muranyi, Arpad
  134. [SI-LIST] Re: Model generation, herbert_lage
  135. [SI-LIST] FWD: Re: Re: HFSS solution issue, Ray Anderson
  136. [SI-LIST] Interference from planar magnetics, Bob Welte
  137. [SI-LIST] SPICE Model for Common Mode Choke, polus
  138. [SI-LIST] How calculate the capacitance between via and plane, Zhangkun
  139. [SI-LIST] Re: How calculate the capacitance between via and plane, Abe Riazi
  140. [SI-LIST] HOW Hspice is Useful in SI analysis for PCB designs??, SUDHEER BS
  141. [SI-LIST] fields question, Yoni Tzafrir
  142. [SI-LIST] test-please ignore, liqun . wang
  143. [SI-LIST] Re: SPICE Model for Common Mode Choke, Ray Anderson
  144. [SI-LIST] IBIS & the Simulator, SiWave
  145. [SI-LIST] [OFF TOPIC] SMD Land patterns, Martin Euredjian
  146. [SI-LIST] Source termination of LVDS drivers, sunil-chandra . kasanyal
  147. [SI-LIST] Re: [IS-LIST] Source termination of LVDS drivers, Robert Kezer
  148. [SI-LIST] Re: Interference from planar magnetics, Bob Welte
  149. [SI-LIST] Re: [OFF TOPIC] SMD Land patterns, cadpro2k
  150. [SI-LIST] Re: IBIS & the Simulator, Angulo, John
  151. [SI-LIST] Different Spice netlists, erno.lahteenmaki
  152. [SI-LIST] SPI 2003 1st announcement, Carla Giachino
  153. [SI-LIST] Autogerb questions, Uzma Khan
  154. [SI-LIST] CMI encoded signal, Bob Patel
  155. [SI-LIST] Re: CMI encoded signal, Ray Anderson
  156. [SI-LIST] Re: Source termination of LVDS drivers, Boris Yost
  157. [SI-LIST] Capacitors UNDER a BGA??, Grasso, Charles
  158. [SI-LIST] Re: Capacitors UNDER a BGA??, Gupta, Deepali
  159. [SI-LIST] impedance matching for high freq PCB, Betty Luk
  160. [SI-LIST] Re: High-Speed GHz differential signals routed Broadside Coupled, Doug Hopperstad
  161. [SI-LIST] Inverter/buffer, hariharan
  162. [SI-LIST] junior designer question, Nico Fleurinck
  163. [SI-LIST] XFP Serial Interface Article (FYI), Lawrence Williams
  164. [SI-LIST] Need help for VCO simulation., Gurumurthy, Radhika
  165. [SI-LIST] EMI fixed by flooding?, Bill Dempsey
  166. [SI-LIST] Re: EMI fixed by flooding?, Vishram Pandit
  167. [SI-LIST] Matching impedance, Bob Patel
  168. [SI-LIST] Re: Different Spice netlists, Clewell, Craig
  169. [SI-LIST] Re: IBIS Models, Charlotte &/or Roy Leventhal
  170. [SI-LIST] How accurate is HSPICE's field solver?, Hassan O. Ali
  171. [SI-LIST] Re: How accurate is HSPICE's field solver?, Clewell, Craig
  172. [SI-LIST] output circuit for 68000 NMOS driver, Peterson, James F (FL51)
  173. [SI-LIST] RMCEMC Bonus Feb Meeting Reminder, Grasso, Charles
  174. [SI-LIST] Conductor Ampacity question, Patrick Codd
  175. [SI-LIST] Re: Matching impedance, Larry Barnes
  176. [SI-LIST] SI engineer seeking employment, Jon Powell
  177. [SI-LIST] test, SDSIGUY
  178. [SI-LIST] Signal Integrity Engineer Available, SDSIGUY



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