Date Index for si-list, 01-2003

[si-list] || [01-2003 Date Index] [01-2003 Thread Index]

[SI-LIST] Happy new year!!!!!!!!!!!!!!!! - Sathish
[SI-LIST] Happy New year. - Inmyung Song
[SI-LIST] problem about resistor on chip - Bi Han
[SI-LIST] Looking for soft copy of old wl gore paper on eye diagrams..... - Michael_Greim
[SI-LIST] FW: Using translated EBD models in Eplanner-scratchpad - Resend - Gupta, Anurag x4500
[SI-LIST] LVDS & TMDS - Ched-Chang Chai
[SI-LIST] Re: LVDS & TMDS - ZL e-Studio
[SI-LIST] More efffects of paths crossing ground plane breaks - Doug Smith
[SI-LIST] USB interconnect question - Robert Sefton
[SI-LIST] Re: Regarding Pull down - Mike Brown
[SI-LIST] about dc-offset compensation in amplifier - Bi Han
[SI-LIST] How to calculate the resistance and inductance of vias - Zhangkun
[SI-LIST] Re: How to calculate the resistance and inductance of vias - Bi Han
[SI-LIST] How to calculate the resistance and inductance of vias - Gregory R Edlund
[SI-LIST] Re: How to calculate the resistance and inductance of vias - Rich Peyton
[SI-LIST] Re: How to calculate the resistance and inductance of vias - Ingraham, Andrew
[SI-LIST] Re: How to calculate the resistance and inductance of vias - Ken Cantrell
[SI-LIST] Re: How to calculate the resistance and inductance of vias - Robert Friedman
[SI-LIST] Using translated EBD models in Eplanner-scratchpad - Resend - Gupta, Anurag x4500
[SI-LIST] Re: How to calculate the resistance and inductance of vias - Steve Corey
[SI-LIST] Re: Using translated EBD models in Eplanner-scratchpad - Resend - danwei xue
[SI-LIST] Re: Regarding Pull down - Adeel Malik
[SI-LIST] Re: Regarding Pull down - Ingraham, Andrew
[SI-LIST] Re: Regarding Pull down - Todd Westerhoff
[SI-LIST] Re: Regarding Pull down - pwelling
[SI-LIST] pcmcia - typical ibis model - k EPD
[SI-LIST] How to calculate the resistance and inductance of vias - Eric Bogatin
[SI-LIST] calculating difference impedance for broadside coupled signals - Sachin Chheda
[SI-LIST] Re: calculating difference impedance for broadside coupled signals - Martyn Gaudion
[SI-LIST] New Article and Class - Scott McMorrow
[SI-LIST] Re: calculating difference impedance for broadside coupled signals - Michael Khusid
[SI-LIST] Wireless board interconnect - John Coupland
[SI-LIST] transmission line equations - Nick Paulter
[SI-LIST] Re: transmission line equations - Doug Brooks
[SI-LIST] Senior Signal Integrity Engineer Position Available - Frank Yuan
[SI-LIST] SI/Timing tool survey - Todd Westerhoff
[SI-LIST] Package model in spectraquest - sudheer_bs
[SI-LIST] Re: SI/Timing tool survey - Robert Haller
[SI-LIST] Re: Package model in spectraquest - John Horner
[SI-LIST] Re: Wireless board interconnect - John Coupland
[SI-LIST] Mentor to XTK translation problem - Perry Qu
[SI-LIST] chip inductors - C Deibele
[SI-LIST] Re: Mentor to XTK translation problem - Perry Qu
[SI-LIST] Re: Mentor to XTK translation problem - Donkle, Steve
[SI-LIST] Re: Wireless board interconnect - Michael Khusid
[SI-LIST] Skew boards - Hora Abu
[SI-LIST] Skew boards - Hora Abu
[SI-LIST] Parallel Resonance of crystall oscillator - Parthasarathy Sampath
[SI-LIST] Re: chip inductors - Morgenstierne, Christian
[SI-LIST] SV: Re: Mentor to XTK translation problem - Anders Ekholm (EAB)
[SI-LIST] Re: SI/Timing tool survey - Peterson, James F (FL51)
[SI-LIST] 10 Gbps Driver/Receiver IBIS model - Gangyao Xiao
[SI-LIST] Re: Mentor to XTK translation problem - Perry Qu
[SI-LIST] Re: How to connect vias to power ground plane? - nsi041350-Roberts
[SI-LIST] Re: chip inductors - Chuck Reynolds
[SI-LIST] Re: How to calculate the resistance and inductance of vias - nsi041350-Roberts
[SI-LIST] Re: 10 Gbps Driver/Receiver IBIS model - Michael Khusid
[SI-LIST] Planar EM solvers? - Fasig, Jonathan L.
[SI-LIST] Re: Parallel Resonance of crystall oscillator - super cop
[SI-LIST] Re: 10 Gbps Driver/Receiver IBIS model - Korcz, Cezary
[SI-LIST] Re: Parallel Resonance of crystall oscillator - ViswanathanRavi
[SI-LIST] Re: Parallel Resonance of crystall oscillator - Bob Weber
[SI-LIST] Re: Parallel Resonance of crystall oscillator - Ray Anderson
[SI-LIST] Re: 10 Gbps Driver/Receiver IBIS model - Peters, Stephen
[SI-LIST] Platform Conference - Beal, Weston
[SI-LIST] Re: (no subject) - Matthew Herndon
[SI-LIST] FR4 non-linear - Loyer, Jeff
[SI-LIST] Re: FR4 non-linear - Scott McMorrow
[SI-LIST] Resistor Calculator - PYHTILA,JOHN (HP-Cupertino,ex1)
[SI-LIST] Re: Resistor Calculator - Martin Euredjian
[SI-LIST] hspice issue - Bi Han
[SI-LIST] Voltage drop across the Inductance - Jayaprakash Balachandran
[SI-LIST] Re: Voltage drop across the Inductance - John Spohnheimer
[SI-LIST] RMCEMC January Meeting Announcement - Charles Grasso
[SI-LIST] Re: Voltage drop across the Inductance - Zabinski, Patrick J.
[SI-LIST] new paper posted - Doug Smith
[SI-LIST] Re: hspice issue - Bi Han
[SI-LIST] vias in flex circuits - Jan Vercammen
[SI-LIST] Ceramic caps - Lucas Bossetti
[SI-LIST] Re: FR4 non-linear - Jim G Roberts
[SI-LIST] Re: Ceramic caps - John Barnes
[SI-LIST] Re: hspice issue - Yu Liu
[SI-LIST] Differential Timing in IBIS - Timothy Coyle
[SI-LIST] Re: (no subject) - summary - Matthew Herndon
[SI-LIST] Re: Parallel Resonance of crystall oscillator - Bi Han
[SI-LIST] clocking using CPLD - hariharan
[SI-LIST] HCSL Ibis Model - Manor, Ben
[SI-LIST] SI with IBIS models for ECL devices. - Paliakara, Vinod
[SI-LIST] Re: Parallel Resonance of crystall oscillator - Lieby David
[SI-LIST] Re: clocking using CPLD - James_R_Jones
[SI-LIST] Re: SI with IBIS models for ECL devices. - David Fogel
[SI-LIST] Re: Parallel Resonance of crystall oscillator - Ed Miguel
[SI-LIST] Re: SI with IBIS models for ECL devices. - Tom Dagostino
[SI-LIST] Job openings at Sigrity - Teo Yatman
[SI-LIST] Re: SI with IBIS models for ECL devices. - David Fogel
[SI-LIST] Re: SI with IBIS models for ECL devices. - Hugo-莊彧宙\(gcn\)
[SI-LIST] Re: SI with IBIS models for ECL devices. - Tom Dagostino
[SI-LIST] Re: SI with IBIS models for ECL devices. - Scott McMorrow
[SI-LIST] Re: SI with IBIS models for ECL devices. - Scott McMorrow
[SI-LIST] [Fwd: Re: Differential Timing in IBIS] - Robert Haller
[SI-LIST] Lumped vs. Distrbuted systems. - Michael Frandsen
[SI-LIST] Re: Resistor Calculator - Claudio Girardi
[SI-LIST] HSTL class-III - rajat . chauhan
[SI-LIST] Re: Lumped vs. Distrbuted systems. - Scott McMorrow
[SI-LIST] Re: Lumped vs. Distrbuted systems. - Ken Cantrell
[SI-LIST] Re: Lumped vs. Distrbuted systems. - Scott McMorrow
[SI-LIST] European IBIS Summit Announcement - Ross, Bob
[SI-LIST] Validate your IBIS models - quickly and completely! - Lynne Green
[SI-LIST] Re: Validate your IBIS models - quickly and completely! - Lynne Green
[SI-LIST] Re: S-parameter use summary - MikonCons
[SI-LIST] looking for IBIS models - Kevin Buchanan
[SI-LIST] ground plane cut-out pattern for SMA connectors - Gregory R Edlund
[SI-LIST] Re: Resistor Calculator - Jeremy Webb
[SI-LIST] Re: SI with IBIS models for ECL devices. - Paliakara, Vinod
[SI-LIST] Re: HSTL class-III - rajat . chauhan
[SI-LIST] Re: Resistor Calculator (off topic) - Claudio Girardi
[SI-LIST] Re: ground plane cut-out pattern for SMA connectors - Loyer, Jeff
[SI-LIST] spice modeling for organic build-up substrates - Javier DeLaCruz
[SI-LIST] Re: spice modeling for organic build-up substrates - Anil Pannikkat
[SI-LIST] Ethernet Magnetic Jacks - Youssef Khalife
[SI-LIST] Hard drive paper posted - Doug Smith
[SI-LIST] DDR skew - chendla
[SI-LIST] bidirectional line driver needed - Nico Fleurinck
[SI-LIST] Re: bidirectional line driver needed - hariharan
[SI-LIST] Re: bidirectional line driver needed - Ingraham, Andrew
[SI-LIST] Re: New Article and Class - Vieira, Keith
[SI-LIST] SI Engineer Job Opening at Stratus in Maynard, MA - Mango, Steve
[SI-LIST] si-list administrivia....... - Ray Anderson
[SI-LIST] Re: bidirectional line driver needed - Muhammad Sagarwala
[SI-LIST] Re: New Article and Class - john lipsius
[SI-LIST] Re: S-parameter use summary - MikonCons
[SI-LIST] Flight time skew due to Dk varation - Perry Qu
[SI-LIST] Re: Flight time skew due to Dk varation - Loyer, Jeff
[SI-LIST] Re: spice modeling for organic build-up substrates - Pat Diao
[SI-LIST] Re: Flight time skew due to Dk varation - Martyn Gaudion
[SI-LIST] chip cap topology - Ed Priest
[SI-LIST] chip cap topology - retry - Ed Priest
[SI-LIST] Re: chip cap topology - retry - Zhiping Yang
[SI-LIST] Re: spice modeling for organic build-up substrates - Javier DeLaCruz
[SI-LIST] Re: spice modeling for organic build-up substrates - Pat Diao
[SI-LIST] Ethernet Magnetic Jacks - Youssef Khalife
[SI-LIST] Re: Ethernet Magnetic Jacks - Mandrusov, Vladimir
[SI-LIST] [SI-LIST]the palcement of bypass/decoupling capacitors - lu Haizhao
[SI-LIST] SDRAM Timing - Martin Euredjian
[SI-LIST] Re: SDRAM Timing - Mike Khusid
[SI-LIST] Re: Ethernet Magnetic Jacks - mmunroe
[SI-LIST] Re: [SI-LIST]the palcement of bypass/decoupling capacitors - istvan novak
[SI-LIST] Any body have gscan & tkdiff on solaris - Bi Han
[SI-LIST] Re: [SI-LIST]the palcement of bypass/decoupling capacitors - Ege Engin
[SI-LIST] HELP - pcb dsd
[SI-LIST] please provide me ibis model of HCPL 6651 ASAP - pcb dsd
[SI-LIST] Combining DC and TRANS analysis - Shee Kian Wong
[SI-LIST] Re: Flight time skew due to Dk varation - Perry Qu
[SI-LIST] RMCEMC January Meeting reminder - Grasso, Charles
[SI-LIST] Re: Combining DC and TRANS analysis - Ingraham, Andrew
[SI-LIST] Re: Combining DC and TRANS analysis - Scott McMorrow
[SI-LIST] Re: Combining DC and TRANS analysis - Scott McMorrow
[SI-LIST] Re: Combining DC and TRANS analysis - Cove, Stephen E
[SI-LIST] Seminar on Embedded Passives - William M. Balliette/AT-Austin/3M/US
[SI-LIST] Coplanar differential signals - Mroczkowski, Jason
[SI-LIST] Re: Coplanar differential signals - Gangyao Xiao
[SI-LIST] Re: Coplanar differential signals - Paul Levin
[SI-LIST] Re: Coplanar differential signals - Nirmal Sharma
[SI-LIST] Simulationsof a connector - Michael Kurten
[SI-LIST] Re: Combining DC and TRANS analysis - Shee Kian Wong
[SI-LIST] Re: Simulationsof a connector - christopher . heard
[SI-LIST] Re: Simulationsof a connector - istvan novak
[SI-LIST] De-coupling capacitor - Pradeep Amrithraj
[SI-LIST] Re: De-coupling capacitor - David Fogel
[SI-LIST] Re: Combining DC and TRANS analysis - Ingraham, Andrew
[SI-LIST] Re: De-coupling capacitor - Tom Dagostino
[SI-LIST] Re: De-coupling capacitor - Pradeep Amrithraj
[SI-LIST] Re: De-coupling capacitor - Ingraham, Andrew
[SI-LIST] Re: De-coupling capacitor - John Barnes
[SI-LIST] Re: De-coupling capacitor - Pradeep Amrithraj
[SI-LIST] Re: [SI-LIST]the palcement of bypass/decoupling capacitors - istvan novak
[SI-LIST] Re: Simulationsof a connector - Robert Haller
[SI-LIST] Re: Simulationsof a connector - Clewell, Craig
[SI-LIST] Re: De-coupling capacitor - ruston, matt
[SI-LIST] Re: De-coupling capacitor - Randol Mark-ryvw50
[SI-LIST] Re: De-coupling capacitor - Larry Smith
[SI-LIST] Re: De-coupling capacitor - Istvan Novak - Board Design Technology
[SI-LIST] Re: De-coupling capacitor - John Barnes
[SI-LIST] Re: De-coupling capacitor - Gupta, Anurag x4500
[SI-LIST] Re: De-coupling capacitor - Raja Patil
[SI-LIST] Re: (no subject) - full summary - Matthew Herndon
[SI-LIST] Re: Simulationsof a connector - Michael Kurten
[SI-LIST] RMCEMC Bonus February meeting - Charles Grasso
[SI-LIST] if any body know abt any seminars in india(Bangalore) - mbestha
[SI-LIST] Re: De-coupling capacitor - Bart Bouma
[SI-LIST] ´ð¸´: Re: [SI-LIST]the palcement of bypass/decoupling capacitors - lu Haizhao
[SI-LIST] Spice-models - erno.lahteenmaki
[SI-LIST] Re: Spice-models - Alicia Corrales Chanca
[SI-LIST] Re: ´ð¸´: Re: [SI-LIST]the palcement of bypass/decoupling capacitors - istvan novak
[SI-LIST] Re: Spice-models - Linnenbruegger Dirk
[SI-LIST] Re: ´ð¸´: Re: [SI-LIST]the palceme nt of bypass/decoupling capacitors - istvan novak
[SI-LIST] Some issues related to spiral inductor modelling. - Bi Han
[SI-LIST] Is-there a Mathcad model available? - Paradis, Daniel
[SI-LIST] si-list still experiencing moderation problems - Ray Anderson
[SI-LIST] FWD: SI Engineer Job Opening at Stratus in Maynard, MA - Ray Anderson
[SI-LIST] FWD: PCD Magazine - Ray Anderson
[SI-LIST] FWD: Re: Ethernet Magnetic Jacks - Ray Anderson
[SI-LIST] FWD: PCB Trace Z, C, & L relationship - Ray Anderson
[SI-LIST] FWD: Routing Differential PECL Signals - Ray Anderson
[SI-LIST] FWD: Beylium Copper - Ray Anderson
[SI-LIST] FWD: Re:_[SI-LIST]the placement of bypass/decoupling capacitors - Ray Anderson
[SI-LIST] FWD: RE: Some issues related to spiral inductor modelling. - Ray Anderson
[SI-LIST] Re: FWD: Berylium Copper - Julian Ferry
[SI-LIST] Re: Berrylium Copper - Ray Anderson
[SI-LIST] Re: FWD: Beylium Copper - Clewell, Craig
[SI-LIST] Re: FWD: Beylium Copper - Clewell, Craig
[SI-LIST] Re: FWD: RE: Some issues related to spiral inductor modelling. - Ji Zheng
[SI-LIST] Re: FWD: PCB Trace Z, C, & L relationship - Larry Smith
[SI-LIST] Re: FWD: PCB Trace Z, C, & L relationship - Larry Smith
[SI-LIST] Re: FWD: PCB Trace Z, C, & L relationship - Peters, Stephen
[SI-LIST] Re: FWD: PCB Trace Z, C, & L relationship - Zhangkun
[SI-LIST] How complete waveform created? - Jack W.C. Lin
[SI-LIST] question on IBIS: rising/falling waveform. - adeel . ahmad
[SI-LIST] Re: question on IBIS: rising/falling waveform. - gaurav . mathur
[SI-LIST] Re: FWD: RE: Some issues related to spiral inductor modelling. - Bi Han
[SI-LIST] help me guys - mbestha
[SI-LIST] over & under shoots - Sajith E K
[SI-LIST] Re: Some issues related to spiral inductor modelling. - Bi Han
[SI-LIST] Re: FWD: RE: Some issues related to spiral inductor modelling. - Swanson, Dan
[SI-LIST] Re: FWD: RE: Some issues related to spiral inductor modelling. - Bi Han
[SI-LIST] Re: FWD: RE: Some issues related to spiral inductor modelling. - Chandrasekhar Arun
[SI-LIST] Re: over & under shoots - James_R_Jones
[SI-LIST] Re: over & under shoots - Ingraham, Andrew
[SI-LIST] HFSS solution issue - Bi Han
[SI-LIST] Re: Question on IBIS: rising/falling waveform - How complete waveform created? - Muranyi, Arpad
[SI-LIST] Re: HFSS solution issue - Swanson, Dan
[SI-LIST] Re: question on IBIS: rising/falling waveform. - Ingraham, Andrew
[SI-LIST] Re: question on IBIS: rising/falling waveform. - herbert_lage
[SI-LIST] Re: over & under shoots - Tom Dagostino
[SI-LIST] Model generation - Bob Patel
[SI-LIST] Re: Model generation - Tom Dagostino
[SI-LIST] Cosmoscope for eye-diagrams ?? - Ray Anderson
[SI-LIST] Re: Cosmoscope for eye-diagrams ?? - Ray Anderson
[SI-LIST] Stub length of a clock - Hora Abu
[SI-LIST] Re: Stub length of a clock - James_R_Jones
[SI-LIST] Re: Question on IBIS: rising/falling waveform - How complete waveform created? - Jack W.C. Lin
[SI-LIST] Re: Question on IBIS: rising/falling waveform - How complete waveform created? - Tom Dagostino
[SI-LIST] Re: HFSS solution issue - Chandrasekhar Arun
[SI-LIST] Re: HFSS solution issue - Xin Wu
[SI-LIST] Re: HFSS solution issue - Xin Wu
[SI-LIST] Steve Wood/TOSHIBA_TEE is out of the office. - Steve . Wood
[SI-LIST] Re: Question on IBIS: rising/falling waveform - H ow complete waveform created? - Muranyi, Arpad
[SI-LIST] Re: over & under shoots - Jim G Roberts
[SI-LIST] Re: Model generation - herbert_lage
[SI-LIST] Re: Stub length of a clock - Jim G Roberts
[SI-LIST] FWD: Re: Re: HFSS solution issue - Ray Anderson
[SI-LIST] Interference from planar magnetics - Bob Welte
[SI-LIST] SPICE Model for Common Mode Choke - polus
[SI-LIST] Re: Interference from planar magnetics - Dennis Schmitz
[SI-LIST] Re: SPICE Model for Common Mode Choke - Dennis Schmitz
[SI-LIST] How calculate the capacitance between via and plane - Zhangkun
[SI-LIST] Re: SPICE Model for Common Mode Choke - Zhangkun
[SI-LIST] Re: How calculate the capacitance between via and plane - hariharan
[SI-LIST] Re: How calculate the capacitance between via and plane - Abe Riazi
[SI-LIST] HOW Hspice is Useful in SI analysis for PCB designs?? - SUDHEER BS
[SI-LIST] Re: Question on IBIS: rising/falling waveform - How complete waveform created? - adeel . ahmad
[SI-LIST] fields question - Yoni Tzafrir
[SI-LIST] test-please ignore - liqun . wang
[SI-LIST] Re: SPICE Model for Common Mode Choke - Ray Anderson
[SI-LIST] IBIS & the Simulator - SiWave
[SI-LIST] Re: How calculate the capacitance between via and plane - Ryu, Chang
[SI-LIST] Re: Interference from planar magnetics - Larry Smith
[SI-LIST] Re: Interference from planar magnetics - steve weir
[SI-LIST] [OFF TOPIC] SMD Land patterns - Martin Euredjian
[SI-LIST] R: [OFF TOPIC] SMD Land patterns - Galli Bruno
[SI-LIST] Source termination of LVDS drivers - sunil-chandra . kasanyal
[SI-LIST] Re: [IS-LIST] Source termination of LVDS drivers - Robert Kezer
[SI-LIST] Re: [OFF TOPIC] SMD Land patterns - Jeff Seeger
[SI-LIST] Re: Interference from planar magnetics - Bob Welte
[SI-LIST] Re: Interference from planar magnetics - Ray Anderson
[SI-LIST] Re: HFSS solution issue - Zhou, Xingling (Mick)
[SI-LIST] Re: [OFF TOPIC] SMD Land patterns - cadpro2k
[SI-LIST] Re: IBIS & the Simulator - Angulo, John
[SI-LIST] Re: IBIS & the Simulator - Todd Westerhoff
[SI-LIST] Re: IBIS & the Simulator - Angulo, John
[SI-LIST] Re: Interference from planar magnetics - steve weir
[SI-LIST] Re: IBIS & the Simulator - SiWave
[SI-LIST] Different Spice netlists - erno.lahteenmaki
[SI-LIST] SPI 2003 1st announcement - Carla Giachino
[SI-LIST] Re: HFSS solution issue - Chandrasekhar Arun
[SI-LIST] Autogerb questions - Uzma Khan
[SI-LIST] CMI encoded signal - Bob Patel
[SI-LIST] Re: CMI encoded signal - Ray Anderson
[SI-LIST] Re: Source termination of LVDS drivers - Boris Yost
[SI-LIST] Re: Source termination of LVDS drivers - Robert Kezer
[SI-LIST] Re: Question on IBIS: rising/falling waveform - How complete waveform created? - Muranyi, Arpad
[SI-LIST] Capacitors UNDER a BGA?? - Grasso, Charles
[SI-LIST] Re: Capacitors UNDER a BGA?? - Gupta, Deepali
[SI-LIST] impedance matching for high freq PCB - Betty Luk
[SI-LIST] Re: Capacitors UNDER a BGA?? - Michael Khusid
[SI-LIST] Re: Question on IBIS: rising/falling waveform - How complete waveform created? - adeel . ahmad
[SI-LIST] Re: High-Speed GHz differential signals routed Broadside Coupled - Doug Hopperstad
[SI-LIST] Inverter/buffer - hariharan
[SI-LIST] junior designer question - Nico Fleurinck
[SI-LIST] Re: junior designer question - Robert Haller
[SI-LIST] New Hardware Job Interview Question - Eitan k
[SI-LIST] XFP Serial Interface Article (FYI) - Lawrence Williams
[SI-LIST] Re: Capacitors UNDER a BGA?? - Lee Ritchey
[SI-LIST] Re: High-Speed GHz differential signals routed Broadside Coupled - Javier DeLaCruz
[SI-LIST] Re: High-Speed GHz differential signals routed Broadside Coupled - Bill Dempsey
[SI-LIST] Need help for VCO simulation. - Gurumurthy, Radhika
[SI-LIST] Re: Need help for VCO simulation. - Parthasarathy Sampath
[SI-LIST] EMI fixed by flooding? - Bill Dempsey
[SI-LIST] Re: impedance matching for high freq PCB - Betty Luk
[SI-LIST] Re: EMI fixed by flooding? - Vishram Pandit
[SI-LIST] Matching impedance - Bob Patel
[SI-LIST] Re: Different Spice netlists - Clewell, Craig
[SI-LIST] Re: IBIS Models - Charlotte &/or Roy Leventhal
[SI-LIST] Re: Different Spice netlists - Linnenbruegger Dirk
[SI-LIST] How accurate is HSPICE's field solver? - Hassan O. Ali
[SI-LIST] Re: How accurate is HSPICE's field solver? - Clewell, Craig
[SI-LIST] Re: Different Spice netlists - Fred Balistreri
[SI-LIST] output circuit for 68000 NMOS driver - Peterson, James F (FL51)
[SI-LIST] Re: Different Spice netlists - Clewell, Craig
[SI-LIST] Re: How accurate is HSPICE's field solver? - Gil Gafni
[SI-LIST] Re: Matching impedance - Jim G Roberts
[SI-LIST] Re: How accurate is HSPICE's field solver? - Scott McMorrow
[SI-LIST] Re: Different Spice netlists - Fred Balistreri
[SI-LIST] RMCEMC Bonus Feb Meeting Reminder - Grasso, Charles
[SI-LIST] Re: Different Spice netlists - Ingraham, Andrew
[SI-LIST] Conductor Ampacity question - Patrick Codd
[SI-LIST] Re: Different Spice netlists - Muranyi, Arpad
[SI-LIST] Re: Matching impedance - Scott McMorrow
[SI-LIST] Re: Different Spice netlists - Clewell, Craig
[SI-LIST] Re: Matching impedance - Larry Barnes
[SI-LIST] SI engineer seeking employment - Jon Powell
[SI-LIST] Re: output circuit for 68000 NMOS driver - Sandy Taylor
[SI-LIST] test - SDSIGUY
[SI-LIST] Signal Integrity Engineer Available - SDSIGUY