FreeLists / si-list / [SI-LIST] Re: SV: Total load capacitance

["Dagostino, Tom" <tom_dagostino@xxxxxxxxxxx>]

I agree with Arpad.  The real environment is a transmission line and the part 
should be spec'ed into that.  I'll add one thing to Arpad's comments.  

Verification of the part's performance in a tester may require it to drive a 
capacitive load (I don't know which ATE system you are using or the load it 
presents to the part.  I would hope it looks like a terminated transmission 
line.).  I would guess the 47 pF 500 Ohm load values written on that cave wall 
in Texas were derived from the input impedance of whatever test system was used 
in the 60s to characterize early RTL, DTL and TTL.  These values have been 
modified over time to reflect better test equipment I would guess or at least 
the understanding of the test engineers about what the part was driving in the 
tester or bench top test equipment.

Is what you are trying to spec the performance into a circuit board or the 
performance into some test system?

Tom Dagostino
Modeling Manager
Mentor Graphics Corp.
SAE
tom_dagostino@xxxxxxxxxx
503-685-1613


-----Original Message-----
From: Muranyi, Arpad [mailto:arpad.muranyi@xxxxxxxxx]
Sent: Thursday, January 10, 2002 11:31 AM
To: si_list
Subject: [SI-LIST] Re: SV: Total load capacitance



All,

I am sorry, but I can't watch this thread go on without saying
something, because I am about to burst...

This idea of estimating the necessary buffer strength by the
total capacitance is very old, and ill fated for high speed
systems.  As someone correctly pointed out, it may only be good
when the edge rates and trace lengths are such that the signal
arrives to all receivers way before the buffer is done switching.
(I am deliberately using these words here, because talking
wavelengths and frequencies may be too mysterious to many).

Unless you are working with such slow buffers (or such
impossibly short distances), you must forget about this
idea all together.

In today's commonly used technology the buffer is done switching
way before the signal arrives at the end of the wire.  This means
that the wire is not a wire, but a transmission line.  If so, the
buffer strength depends on the impedance of the T-line, or the
termination style (none, parallel, series).

The load capacitance at the end of the line has not much to do with
sizing the buffer.  Consider this equivalent circuit for a point to
to point topology.  Driver - T_line - Receiver, where the driver
is a 10 Ohm Thevenin circuit, i.e. an ideal step function source
with a 10 Ohm series resistor, the T_line is a 50 Ohm series
resistor (yes series R, because we are talking about the condition
while the signal is propagating in the line), and the receiver is
a 10 pF capacitance to ground.

If you look at this circuit you will see that it is a simple RC circuit.
The waveform on the capacitance will be an exponentially shaped curve,
and its time constant is RC to reach the 63% point (50+10)*10e-12 = 0.6ns.
Now, if you remove the 10 Ohm Thevenin resistor from the circuit, i.e.
turn the driver into a superconductor, the equation changes to:
50*10e-12 = 0.5ns!  Was it worth it?  From this you can see that the
edge rate at the receiver will not depend too much on the drive
strength, but more on the ZC relationship between the T-line
impedance and the input capacitance.

Also, the amount of time the signal needs to travel along the T-line
is determined by Maxwell's wave equations, which are completely
independent from the driver strength.

The driver strength is only important when you start figuring out
overshoot for unterminated systems, or signal swing for parallel
terminated systems.  In those cases the T-line and/or the parallel
termination look like a resistor to the driver, and we are talking
about voltage dividers.

The only place the capacitance may come into effect is of you have
(evenly) distributed loads (receivers) along the T-line.  That will
reduce the effective impedance of the T-line, but this, again is
like a resistive load to the buffer with a lowered value...

So, in short, forget about capacitive loading in your calculations!

Arpad Muranyi
Intel Corporation
==================================================================

-----Original Message-----
From: Bob Patel [mailto:whizplayer@xxxxxxxxx]
Sent: Thursday, January 10, 2002 9:19 AM
To: Ingraham, Andrew
Cc: si_list
Subject: [SI-LIST] Re: SV: Total load capacitance



 Hi! Andrew, This load capacitance estimate is for determining the drive
strenght needed for an ASIC I/O. This capacitance is beiong calculated wiht
the fact that I need to maintain the characteristic impedance to 50ohms and
this way I ensure that the driver can source/sink the required amount of
current in order to maintain the rise and fall times of the signal.
Thanks
Bob
  "Ingraham, Andrew" <Andrew.Ingraham@xxxxxxxxxx> wrote: > Hi! Anders, Even
if I take a transmission line
> approach the total capacitance faced by the driver
> will always be there i.e. even if the edge rates are
> faster and the driver is weak then the rise & fall
> time will not be maintained at the receiver and if the
> C is too large then the driver may not be able to
> drive it above Voh. SO, either way this lumped
> capacitance approach has to be taken into account to
> determine the drive needed.

That depends. Take the 1000 meter cable with Zo = 50 ohms, and put a 50
ohm load on the end of it. Driving it, you can't tell if it's 0 meters
or 1000 meters long. It looks the same to the driver. (Ignoring
discontinuities, non-ideal loads, and cable losses.)

If it didn't have the 50 ohm load, the situation is different. If the
cable is long enough, the initial edge rates would be determined by the
ability of the driver to drive the characteristic impedance of the
cable; but eventually the reflections would come back and modify the
waveforms in some way that you can't quantify by simply adding up the
cable capacitance. If the signal is periodic and the electrical length
is an exact multiple of half the repetition rate, then the amplitude
(and therefore edge rates) might be enhanced by the reflections. If it
is an odd multiple of a quarter of the repetition rate, the reflection
might kill the edge rates.

The answer to your question also depends on what you need the
capacitance estimate for, i.e., power estimation, vs. output levels or
edge rates.

Finally, I would think that Cout of the driver has already been
accounted for so you don't need to include it, but check with the ASIC
vendor to be sure.

Regards,
Andy
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