FreeLists / si-list / [SI-LIST] Re: IBIS Driver Models, Simulators and CComp

["Muranyi, Arpad" <arpad.muranyi@xxxxxxxxx>]

Todd,

You describe exactly what I have been preaching in my IBIS classes
for several years now.

Regarding your double counting question, there is a fairly simple
trick you can do in the simulator's algorithm that can make that
capacitor only visible when you look into the buffer from the outside
without loading the V-t curves which already include its effects.

I explained this to Avanti's engineer (Nik) when he was first approached
me, and I know for sure that the HSPICE B-element does this correctly.  I
also talked about this subject with Bob Ross, and he also confirmed that
Interconnectix implemented this correctly also.  So there are tools out
there which do it right.  I do not have information about others.

Regarding the variability of the value of C_comp when the buffer
is driving or receiving, you are also correct in your observation.
It does depend on that as well as voltage, so a single value C_comp
really doesn't cut it.  For more precise modeling we would need
multiple curves (C vs. V).

There is one more thing you didn't mention.  The capacitance needs
to be split between the output pad, supply, and ground rails.  One
capacitor to GND(? IBIS doesn't define where to connect it...) doesn't
do you any good if the return currents are also of a concern to you.
That is why I wrote a BIRD, and that is why HSPICE already has that
bird implemented in the B-element.  And again, I am not able to comment
on any other tool.

Arpad Muranyi
Intel Corporation
===================================================================


-----Original Message-----
From: Todd Westerhoff [mailto:twester@xxxxxxxxxxx]
Sent: Wednesday, January 09, 2002 2:47 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] IBIS Driver Models, Simulators and CComp



Hi all,

We've been doing an investigation recently, comparing IBIS models and
simulation results to their HSpice counterparts.  One of the things that has
emerged as a focal point is the concept of Ccomp (the die capacitance) and
how the IBIS simulator handles it for a driving output.

Ccomp (as I understand it) is meant to represent the intrinsic parasitics of
the I/O cell.  As such, it isn't anything that can be precisely identified
in the Spice model of the I/O - rather, Ccomp models the cumulative effect
of a bunch of things.  That being the case, the V-T curves created for the
IBIS model using Spice will already have the effect of Ccomp included.  If
the IBIS simulator adds a Ccomp capacitor across the IBIS driver's output,
the effect of Ccomp may be "double-counted" when the device is driving.

On the other hand, if the capacitor is not added to the circuit - then the
reflections off the driver will be incorrect, because the driver's output
capacitance will not be modeled.

So the question(s) are -

a) Have other people run into this issue?
b) I suspect the handling of Ccomp for an IBIS driver is EDA tool dependent.
Does anyone know how the different tools handle this?
c) Are there applications > 150 MHz where people are using IBIS and HSpice
interchangably?  If so, how are the correlation issues between the two
simulators managed?

One problem that seems especially insidious (we're still not sure of exactly
what's going on) is that we have a bidirectional I/O whose effective
capacitance seems to be different in the driving and tri-stated conditions.
Given that IBIS allows only one value for Ccomp, that makes correlation even
more challenging.

All responses, public and private - are both welcomed and appreciated.

Todd.


Todd Westerhoff
SI Engineer - Hammerhead Networks
5 Federal Street - Billerica, MA - 01821
email:twester@xxxxxxxxxxx - ph: 978-671-5084
============================================

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 Ain't that America, we're something to see
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