[PCB_FORUM] Re: tangential vias DRCs not behaving as expected
- From: "Jean Bratton" <jean.bratton@xxxxxxxxxxxxxx>
- To: <icu-pcb-forum@xxxxxxxxxxxxx>
- Date: Thu, 1 Sep 2005 08:34:16 -0700
Yes, but apparently when one of the "pads" is a via, the center of the
via must actually fall within the smt land pad, which isn't what we
have.
Thanks, though!
________________________________
From: icu-pcb-forum-bounce@xxxxxxxxxxxxx
[mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of Julian
Ungureanu (jungurea)
Sent: Thursday, September 01, 2005 11:10 AM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Re: tangential vias DRCs not behaving as expected
Have you tried pad/pad direct connect , under net_physical_type?
Julian
________________________________
From: icu-pcb-forum-bounce@xxxxxxxxxxxxx
[mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of Gary MacIndoe
Sent: Thursday, September 01, 2005 7:59 AM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Re: tangential vias DRCs not behaving as expected
Jean,
When I wanted to do something like this in the past, I would give the
constraint area shape a net_spacing_property with the Via to Pin value
as a negative number. You may have to give it a larger negative value
than you would think, I would just give it -100 mils. I haven't used
this method for a few versions, but I would hope that it still works.
Gary E. MacIndoe
PCB Design Engineer
Advanced Micro Devices
Longmont, Colorado
________________________________
From: icu-pcb-forum-bounce@xxxxxxxxxxxxx
[mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of Jean Bratton
Sent: Wednesday, August 31, 2005 6:46 PM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] tangential vias DRCs not behaving as expected
Hi all,
I tried logging onto SourceLink, but it appears they may be down. If
anyone can shed some light on this please do.
The following is an oversimplified example of a problem we're having. In
some areas we need to allow vias to be tangent to, or slightly
overlapping pads. In other areas we do not want that. The blue line is a
constraint area with a net_spacing_property of tangent_ok. The spacing
assignment table assigns a rule, also called tangent_ok, which is a copy
of the DEFAULT rule except that same_net_drc is set to off. As you see,
we still get drc's. If, however, we change the DEFAULT rule to set
same_net_drc to off, then the drc's go away. But, of course, they go
away for both cases, not just the ones in the constraint area. I've
attached this little board file to the mail in case anyone has a few
minutes to play with this and see if we're doing something wrong.
Thanks for any help,
Jean
Jean Bratton
Sr. Printed Circuit Designer
Freedom CAD Services, Inc.
603-864-1300 x1349
