[PCB_FORUM] Re: Removing unused pad rings on inner layers DURING design...
From: chris.ball@xxxxxxxxx
To: icu-pcb-forum@xxxxxxxxxxxxx
Date: Fri, 1 Apr 2005 11:10:29 -0400
Both good points.
Carl is stressing the fact that DRILL size is not the same as FINISHED HOLE
SIZE (after plating). For internal layers, you need to focus on drill size.
If you specify a 10mil finished hole size on the via, then make sure your
internal pad is upsized to the actual drilled hole.
You might get by without worrying about adding std. mfg. tol. Depends. If
you have a min clearance for higher voltage potential, then you'd want to
add it in. If your electrical spacing requirements can live with min
spacing minus mfg.tol., then you're OK (I think).
-Chris
"Austin Franklin"
<austin@xxxxxxxxxxxx> @ To:
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[PCB_FORUM] Re: Removing unused
pad rings on inner
layers DURING design...
04/01/2005 09:48 AM
Please respond to
icu-pcb-forum
Hi Carl,
> I'm sure most of you are aware of this but when you talk about
> making a pad size the size of the drill you need to consider that
> pad size as the actual drill bit size not finished drill + the
> standard manufacturing tolerances. Then you would apply that
> minimum clearance to that pad shape.
I think you want to increase the "pad" size larger than the drill size by
that "standard manufacturing tolerance" (for me, that would be 10 mils plus
3 mils) so that you can use the default trace to via clearance. If you
make
the pad the size of the drill, then you have to increase the trace to via
clearance to include this "standard manufacturing tolerance", which would
then apply to every trace to via, not just the ones with the pads
"removed".
I agree, that making a via with no "regular" internal pads, and then
running
a skill script to add the "regular" pads to places where connections were
made is a great idea, and would make this issue really easy to solve.
Regards,
Austin
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