Posts for si-list, 12-2007

Browse: Last Month: 11-2007 Main Archive Page Next Month: 01-2008

» [SI-LIST] welcome to our website:www.shijishuma.com -
» [SI-LIST] welcome to our website:www.shijishuma.com -
» [SI-LIST] Re: RLGC Matrix -
» [SI-LIST] test -
» [SI-LIST] Re: Books on PLL design and measurements -
» [SI-LIST] Re: CML versus ECL/PECL -
» [SI-LIST] Re: CML versus ECL/PECL -
» [SI-LIST] Re: RLGC Matrix -
» [SI-LIST] RLGC Matrix -
» [SI-LIST] Re: S parameter to time domain signal -
» [SI-LIST] Re: S parameter to time domain signal -
» [SI-LIST] Re: S parameter to time domain signal -
» [SI-LIST] Books on PLL design and measurements -
» [SI-LIST] Re: Pk-Pk jitter -
» [SI-LIST] Chris Heard is out of the office. -
» [SI-LIST] Re: si-list Digest V7 #422 -
» [SI-LIST] Re: si-list Digest V7 #422 -
» [SI-LIST] Re: Draft Touchstone 2.0 document available -
» [SI-LIST] Re: op07 IBIS Model -
» [SI-LIST] op07 IBIS Model -
» [SI-LIST] Touchstone Version 2.0 Proposal for S12/S21 Ordering -
» [SI-LIST] Re: Draft Touchstone 2.0 document available -
» [SI-LIST] Re: Draft Touchstone 2.0 document available -
» [SI-LIST] Re: Pk-Pk jitter -
» [SI-LIST] Re: Pk-Pk jitter -
» [SI-LIST] Pk-Pk jitter -
» [SI-LIST] Re: About jitter simulation -
» [SI-LIST] About jitter simulation -
» [SI-LIST] Re: S parameter to time domain signal -
» [SI-LIST] Re: S parameter to time domain signal -
» [SI-LIST] Re: Safe Operating Area from IBIS -
» [SI-LIST] Re: Need PCI Express HSPICE model -
» [SI-LIST] Re: Safe Operating Area from IBIS -
» [SI-LIST] Safe Operating Area from IBIS -
» [SI-LIST] CML versus ECL/PECL -
» [SI-LIST] Need PCI Express HSPICE model -
» [SI-LIST] Re: S parameter to time domain signal -
» [SI-LIST] ebd simulation in xtk -
» [SI-LIST] Doubt in SSTL_18 dc specPRA -
» [SI-LIST] Re: AW: Re: ESD on center pin of 6VDC jack input. -
» [SI-LIST] Re: S parameter to time domain signal -
» [SI-LIST] Re: S parameter to time domain signal -
» [SI-LIST] Re: S parameter to time domain signal -
» [SI-LIST] Re: S parameter to time domain signal -
» [SI-LIST] Re: S parameter to time domain signal -
» [SI-LIST] Re: S parameter to time domain signal -
» [SI-LIST] Re: S parameter to time domain signal -
» [SI-LIST] S parameter to time domain signal -
» [SI-LIST] Re: internal time step too small error in transient analysis -
» [SI-LIST] AW: Re: ESD on center pin of 6VDC jack input. -
» [SI-LIST] Re: internal time step too small error in transient analysis -
» [SI-LIST] Re: ESD on center pin of 6VDC jack input. -
» [SI-LIST] Re: internal time step too small error in transient analysis -
» [SI-LIST] ESD on center pin of 6VDC jack input. -
» [SI-LIST] internal time step too small error in transient analysis -
» [SI-LIST] Re: PCB trade off -
» [SI-LIST] PCB trade off -
» [SI-LIST] 答复: VRM -
» [SI-LIST] Re: VRM -
» [SI-LIST] Re: VRM -
» [SI-LIST] VRM -
» [SI-LIST] Re: Draft Touchstone 2.0 document available -
» [SI-LIST] Re: time-constant=2.3*Z0*CL -
» [SI-LIST] Re: time-constant=2.3*Z0*CL -
» [SI-LIST] time-constant=2.3*Z0*CL -
» [SI-LIST] Re: Diode Termination -
» [SI-LIST] Re: Diode Termination -
» [SI-LIST] Diode Termination -
» [SI-LIST] Free: Spice post-processing environment -
» [SI-LIST] Re: Draft Touchstone 2.0 document available -
» [SI-LIST] Re: Draft Touchstone 2.0 document available -
» [SI-LIST] Draft Touchstone 2.0 document available -
» [SI-LIST] flat cable model -
» [SI-LIST] Re: : IBIS Vs SPICE matching issue -
» [SI-LIST] : IBIS Vs SPICE matching issue -
» [SI-LIST] Re: Signal crossing Split plane -
» [SI-LIST] Re: Fw: si-list Digest V7 #410 -
» [SI-LIST] Re: Fw: si-list Digest V7 #410 -
» [SI-LIST] Fw: si-list Digest V7 #410 -
» [SI-LIST] Re: Passivity/Causality -
» [SI-LIST] S-par and Spice -
» [SI-LIST] Re: Passivity/Causality -
» [SI-LIST] Passivity/Causality -
» [SI-LIST] Re: Signal crossing Split plane -
» [SI-LIST] Re: Signal crossing Split plane -
» [SI-LIST] Re: Signal crossing Split plane -
» [SI-LIST] a technique for injecting noise for troubleshooting -
» [SI-LIST] Re: Definition of "crosstalk loss" ?? -
» [SI-LIST] Re: Definition of "crosstalk loss" ?? -
» [SI-LIST] Re: Definition of "crosstalk loss" ?? -
» [SI-LIST] Re: Definition of "crosstalk loss" ?? -
» [SI-LIST] Definition of "crosstalk loss" ?? -
» [SI-LIST] Re: time domain simulation of s-parameter -
» [SI-LIST] Re: time domain simulation of s-parameter -
» [SI-LIST] Re: Signal crossing Split plane -
» [SI-LIST] time domain simulation of s-parameter -
» [SI-LIST] Re: How many bond-wires to make a good PDS? -
» [SI-LIST] Re: time domain simulation of s-parameter -
» [SI-LIST] Re: FW: New and latest reference on "Jitter, Noise, and Signal Integrity at High-Speed" -
» [SI-LIST] Re: FW: New and lastest reference on "Jitter, Noise, and Signal Integrity at High-Speed" -
» [SI-LIST] Re: FW: New and lastest reference on "Jitter, Noise, and Signal Integrity at High-Speed" -
» [SI-LIST] Re: Signal crossing Split plane -
» [SI-LIST] Re: fiber-weave effect alive and well? -
» [SI-LIST] Re: fiber-weave effect alive and well? -
» [SI-LIST] Re: fiber-weave effect alive and well? -
» [SI-LIST] Re: fiber-weave effect alive and well? -
» [SI-LIST] Re: How many bond-wires to make a good PDS? -
» [SI-LIST] FW: New and lastest reference on "Jitter, Noise, and Signal Integrity at High-Speed" -
» [SI-LIST] Re: Signal crossing Split plane -
» [SI-LIST] How many bond-wires to make a good PDS? -
» [SI-LIST] Re: time domain simulation of s-parameter -
» [SI-LIST] Re: Signal crossing Split plane -
» [SI-LIST] Re: Signal crossing Split plane -
» [SI-LIST] Re: fiber-weave effect alive and well? -
» [SI-LIST] Re: fiber-weave effect alive and well? -
» [SI-LIST] Re: Signal crossing Split plane -
» [SI-LIST] Re: Overshoot/undershoot for IO buffer -
» [SI-LIST] Re: fiber-weave effect alive and well? -
» [SI-LIST] Re: time domain simulation of s-parameter -
» [SI-LIST] Re: fiber-weave effect alive and well? -
» [SI-LIST] Re: fiber-weave effect alive and well? -
» [SI-LIST] Re: Overshoot/undershoot for IO buffer -
» [SI-LIST] Re: fiber-weave effect alive and well? -
» [SI-LIST] Re: Overshoot/undershoot for IO buffer -
» [SI-LIST] Re: Overshoot/undershoot for IO buffer -
» [SI-LIST] New and lastest reference on "Jitter, Noise, and Signal Integrity at High-Speed" -
» [SI-LIST] 答复: Xtalk from vertical via to horizontal trace -
» [SI-LIST] Re: Signal crossing Split plane -
» [SI-LIST] Re: Signal crossing Split plane -
» [SI-LIST] Re: Signal crossing Split plane -
» [SI-LIST] Re: Overshoot/undershoot for IO buffer -
» [SI-LIST] Xtalk from vertical via to horizontal trace -
» [SI-LIST] Overshoot/undershoot for IO buffer -
» [SI-LIST] Re: Signal crossing Split plane -
» [SI-LIST] Re: time domain simulation of s-parameter -