Posts for si-list, 12-2005

Browse: Last Month: 11-2005 Main Archive Page Next Month: 01-2006

» [SI-LIST] Re: PCI-X 1.0a simulation -
» [SI-LIST] Re: PCI-X 1.0a simulation -
» [SI-LIST] Unsubscribe - 2nd attempt -
» [SI-LIST] Re: PCI-X 1.0a simulation -
» [SI-LIST] Re: Selection of Minimum Coupled Length in Cadence SPECCTRAQuest -
» [SI-LIST] Re: Selection of Minimum Coupled Length in Cadence SPECCTRAQuest -
» [SI-LIST] Re: PCI-X 1.0a simulation -
» [SI-LIST] Re: Test DDR -
» [SI-LIST] Re: Test DDR -
» [SI-LIST] Re: Test DDR -
» [SI-LIST] Test DDR -
» [SI-LIST] Selection of Minimum Coupled Length in Cadence SPECCTRAQuest -
» [SI-LIST] Re: PCI-X 1.0a simulation -
» [SI-LIST] Re: Taking SI and timing specs at face value -
» [SI-LIST] Taking SI and timing specs at face value -
» [SI-LIST] Re: FW: Re: Microstrip/Stripline -
» [SI-LIST] Re: Hspice 2D Field Solver Vs. XFX -
» [SI-LIST] Re: PCI-X 1.0a simulation -
» [SI-LIST] Re: PCI-X 1.0a simulation -
» [SI-LIST] Re: PCI-X 1.0a simulation -
» [SI-LIST] Re: IBIS models needed -
» [SI-LIST] Re: PCI-X 1.0a simulation -
» [SI-LIST] Re: PCI-X 1.0a simulation -
» [SI-LIST] Re: PCI-X 1.0a simulation -
» [SI-LIST] Re: PCI-X 1.0a simulation -
» [SI-LIST] PCI-X 1.0a simulation -
» [SI-LIST] Re: IBIS models needed -
» [SI-LIST] IBIS models needed -
» [SI-LIST] Re: Power Integrity- How to set Z target -
» [SI-LIST] Power Integrity- How to set Z target -
» [SI-LIST] Jon Powell -
» [SI-LIST] Unsubscribe -
» [SI-LIST] Re: Hspice 2D Field Solver Vs. XFX -
» [SI-LIST] Re: Hspice 2D Field Solver Vs. XFX -
» [SI-LIST] Hspice 2D Field Solver Vs. XFX -
» [SI-LIST] Hspice 2D EM Sim Vs. XFX 2D EM Sim -
» [SI-LIST] Re: XAUI -
» [SI-LIST] Re: XAUI -
» [SI-LIST] Re: XAUI -
» [SI-LIST] Re: XAUI -
» [SI-LIST] Re: XAUI -
» [SI-LIST] Re: sorting thru the junk mail -
» [SI-LIST] Re: sorting thru the junk mail -
» [SI-LIST] Re: sorting thru the junk mail -
» [SI-LIST] Re: Copper atom density -
» [SI-LIST] Re: XAUI -
» [SI-LIST] Re: sorting thru the junk mail -
» [SI-LIST] Re: sorting thru the junk mail -
» [SI-LIST] Re: XAUI -
» [SI-LIST] Re: Happy Holidays -
» [SI-LIST] Re: sorting thru the junk mail -
» [SI-LIST] Re: sorting thru the junk mail -
» [SI-LIST] Re: Calling subcircuits in HSpice -
» [SI-LIST] Re: how to evaluate the lead inductance of chippackages -
» [SI-LIST] Re: Calling subcircuits in HSpice -
» [SI-LIST] Re: how to evaluate the lead inductance of chippackages -
» [SI-LIST] Re: Calling subcircuits in HSpice -
» [SI-LIST] XAUI -
» [SI-LIST] Re: Calling subcircuits in HSpice -
» [SI-LIST] Re: Calling subcircuits in HSpice -
» [SI-LIST] Calling subcircuits in HSpice -
» [SI-LIST] Re: Happy Holidays -
» [SI-LIST] Re: sorting thru the junk mail -
» [SI-LIST] Re: Rs in W-element -
» [SI-LIST] Re: Rs in W-element -
» [SI-LIST] Re: Happy Holidays -
» [SI-LIST] Re: sorting thru the junk mail -
» [SI-LIST] Re: Rs in W-element -
» [SI-LIST] Rs in W-element -
» [SI-LIST] Re: Happy Holidays -
» [SI-LIST] Happy Holidays -
» [SI-LIST] sorting thru the junk mail -
» [SI-LIST] Re: Embedded Microstrip -
» [SI-LIST] Re: IBIS Models for the Devices working at GHz speed -
» [SI-LIST] Re: Question about termination of transmission line -
» [SI-LIST] Re: how to evaluate the lead inductance of chip packages -
» [SI-LIST] Re: how to evaluate the lead inductance of chip packages -
» [SI-LIST] Question about termination of transmission line -
» [SI-LIST] Re: Microstrip/Stripline -
» [SI-LIST] how to evaluate the lead inductance of chip packages -
» [SI-LIST] Re: Timing analysis -
» [SI-LIST] Re: IBIS Models for the Devices working at GHz speed -
» [SI-LIST] Re: Timing analysis -
» [SI-LIST] Embedded Microstrip -
» [SI-LIST] Re: Microstrip/Stripline -
» [SI-LIST] Re: Microstrip/Stripline -
» [SI-LIST] IBIS Models for the Devices working at GHz speed -
» [SI-LIST] Re: Signal Integrity Job Opening -
» [SI-LIST] Signal Integrity Job Opening -
» [SI-LIST] Re: Microstrip/Stripline -
» [SI-LIST] Re: Dielctric loss microstip/stripline -
» [SI-LIST] Re: Dielctric loss microstip/stripline -
» [SI-LIST] Dielctric loss microstip/stripline -
» [SI-LIST] E1 EMI protection -
» [SI-LIST] Re: Microstrip/Stripline -
» [SI-LIST] FW: Re: Microstrip/Stripline -
» [SI-LIST] Re: Microstrip/Stripline -
» [SI-LIST] Re: Pin Type Scope ground -
» [SI-LIST] Re: Timing analysis -
» [SI-LIST] Antwort: Re: Adding a capacitance between 2 transmission lines -
» [SI-LIST] Antwort: Re: Adding a capacitance between 2 transmission lines -
» [SI-LIST] Adding a capacitance between 2 transmission lines -
» [SI-LIST] Re: Microstrip/Stripline -
» [SI-LIST] Re: Microstrip/Stripline -
» [SI-LIST] Microstrip/Stripline -
» [SI-LIST] Re: Timing analysis -
» [SI-LIST] Re: Pin Type Scope ground -
» [SI-LIST] Re: Pin Type Scope ground -
» [SI-LIST] Re: Pin Type Scope ground -
» [SI-LIST] Pin Type Scope ground -
» [SI-LIST] Re: Question about Echo cancellation testing -
» [SI-LIST] Question about Echo cancellation testing -
» [SI-LIST] R: I/O Buffer in HSpice -
» [SI-LIST] Re: DC resistance of the Power Supply on PCB -
» [SI-LIST] GerbTool ACR question -
» [SI-LIST] Re: Impedance matching -
» [SI-LIST] Re: Impedance matching -
» [SI-LIST] Impedance matching -
» [SI-LIST] Impedance matching -
» [SI-LIST] Re: PC debug port pinout? -
» [SI-LIST] Re: PC debug port pinout? -
» [SI-LIST] Re: PC debug port pinout? -
» [SI-LIST] PC debug port pinout? -
» [SI-LIST] Re: Timing analysis -
» [SI-LIST] I/O Buffer in HSpice -
» [SI-LIST] Re: Q on V_fixture in IBIS model. -
» [SI-LIST] Timing analysis -
» [SI-LIST] Re: 4-port node numbering -
» [SI-LIST] development of test method standards to characterize probes -
» [SI-LIST] Re: effects of propagation time with respect to rise time -
» [SI-LIST] Re: 4-port node numbering -
» [SI-LIST] Re: Q on V_fixture in IBIS model. -
» [SI-LIST] Q on V_fixture in IBIS model. -
» [SI-LIST] Re: Use of Yahoo and other non-specific email accounts -
» [SI-LIST] Re: effects of propagation time with respect to rise time -
» [SI-LIST] Re: Hi -
» [SI-LIST] Re: 4-port node numbering -
» [SI-LIST] effects of propagation time with respect to rise time -
» [SI-LIST] Re: 4-port node numbering -
» [SI-LIST] Re: 4-port node numbering -
» [SI-LIST] Re: 4-port node numbering -
» [SI-LIST] Re: 4-port node numbering -
» [SI-LIST] Re: 4-port node numbering -
» [SI-LIST] 4-port node numbering -
» [SI-LIST] Reminder: IEEE EMCS Santa Clara Valley Chapter meeting, 12-13-05 -
» [SI-LIST] Re: Microstrip/Stripline -
» [SI-LIST] Re: Microstrip/Stripline -
» [SI-LIST] Re: Microstrip/Stripline -
» [SI-LIST] Re: Logic Analyzer headers XAUI & PCI-E -
» [SI-LIST] Re: Microstrip/Stripline -
» [SI-LIST] Re: Microstrip/Stripline -
» [SI-LIST] Re: Firewire 1394 eye mask -
» [SI-LIST] Re: Hi -
» [SI-LIST] Firewire 1394 eye mask -
» [SI-LIST] Logic Analyzer headers XAUI & PCI-E -
» [SI-LIST] Re: Microstrip/Stripline -
» [SI-LIST] Re: Use of Yahoo and other non-specific email accounts -
» [SI-LIST] Re: Microstrip/Stripline -
» [SI-LIST] Re: USB waveform -
» [SI-LIST] USB waveform -
» [SI-LIST] Hi -
» [SI-LIST] Re: Use of Yahoo and other non-specific email accounts -
» [SI-LIST] Re: Use of Yahoo and other non-specific email accounts -
» [SI-LIST] Re: Microstrip/Stripline -
» [SI-LIST] Microstrip/Stripline -
» [SI-LIST] Re: Use of Yahoo and other non-specific email accounts -
» [SI-LIST] Re: Use of Yahoo and other non-specific email accounts -
» [SI-LIST] Re: Use of Yahoo and other non-specific email accounts -
» [SI-LIST] Re: Use of Yahoo and other non-specific email accounts -
» [SI-LIST] Re: Use of Yahoo and other non-specific email accounts -
» [SI-LIST] Re: Use of Yahoo and other non-specific email accounts -
» [SI-LIST] Re: Use of Yahoo and other non-specific email accounts -
» [SI-LIST] Use of Yahoo and other non-specific email accounts -
» [SI-LIST] Re: Use of Yahoo and other non-specific email accounts -
» [SI-LIST] Re: Use of Yahoo and other non-specific email accounts -
» [SI-LIST] Re: Use of Yahoo and other non-specific email accounts -
» [SI-LIST] Re: Use of Yahoo and other non-specific email accounts -
» [SI-LIST] Re: Use of Yahoo and other non-specific email accounts -
» [SI-LIST] Re: Use of Yahoo and other non-specific email accounts -
» [SI-LIST] Re: Use of Yahoo and other non-specific email accounts -
» [SI-LIST] Re: Use of Yahoo and other non-specific email accounts -
» [SI-LIST] Re: Use of Yahoo and other non-specific email accounts -
» [SI-LIST] Use of Yahoo and other non-specific email accounts -
» [SI-LIST] Re: Via inside SMD discrete -
» [SI-LIST] Re: Via inside SMD discrete -
» [SI-LIST] High Aspect Ratio Problem in HFSS 9.0 -
» [SI-LIST] Re: Question of taking measurement. Thanks. -
» [SI-LIST] Re: Question of taking measurement. Thanks. -
» [SI-LIST] Re: MLF packages -
» [SI-LIST] Re: Question of taking measurement. Thanks. -
» [SI-LIST] Re: Via inside SMD discrete -
» [SI-LIST] Application of copper tape for experimental use -
» [SI-LIST] New Member -
» [SI-LIST] Via inside SMD discrete -
» [SI-LIST] Re: MLF packages -
» [SI-LIST] Re: MLF packages -
» [SI-LIST] Re: Question of taking measurement. Thanks. -
» [SI-LIST] Question of taking measurement. Thanks. -
» [SI-LIST] Re: Back of the envelope termination resistor calculation -
» [SI-LIST] Re: MLF packages -
» [SI-LIST] Re: Trace bandwidth -
» [SI-LIST] Re: Back of the envelope termination resistor calculation -
» [SI-LIST] Re: Back of the envelope termination resistor calculation -
» [SI-LIST] Back of the envelope termination resistor calculation -
» [SI-LIST] Signal Integrity, Package design project in Santa Clara -
» [SI-LIST] Re: Gigabit traces on Backplane -
» [SI-LIST] Re: Impedance control -
» [SI-LIST] Re: MLF packages -
» [SI-LIST] MLF packages -
» [SI-LIST] Re: Gigabit traces on Backplane -
» [SI-LIST] Re: Impedance control -
» [SI-LIST] Gigabit traces on Backplane -
» [SI-LIST] Trace bandwidth -
» [SI-LIST] Impedance control -
» [SI-LIST] Re: pcb board capacitors -
» [SI-LIST] Re: pcb board capacitors -
» [SI-LIST] Re: pcb board capacitors -
» [SI-LIST] Re: CR-5000 Lightning -
» [SI-LIST] CR-5000 Lightning -
» [SI-LIST] Re: pcb board capacitors -
» [SI-LIST] Re: pcb board capacitors -
» [SI-LIST] Re: pcb board capacitors -
» [SI-LIST] validation help -
» [SI-LIST] stack up design with a field solver -
» [SI-LIST] Re: pcb board capacitors -
» [SI-LIST] Re: pcb board capacitors -
» [SI-LIST] pcb board capacitors -
» [SI-LIST] Mobile DDR specifications. -
» [SI-LIST] Re: NEXT and FEXT: Question on relative levels -
» [SI-LIST] Re: NEXT and FEXT: Question on relative levels -
» [SI-LIST] Re: NEXT and FEXT: Question on relative levels -
» [SI-LIST] Re: DC resistance of the Power Supply on PCB -
» [SI-LIST] Re: IBIS question -
» [SI-LIST] IBIS question -