Posts for si-list, 11-2011

Browse: Last Month: 10-2011 Main Archive Page Next Month: 12-2011

» [SI-LIST] Re: what level of overshoot is acceptalbe - WANG Zhenwei
» [SI-LIST] Re: what level of overshoot is acceptable - Tom Dagostino
» [SI-LIST] Re: what level of overshoot is acceptalbe - ERIK KUNDRO
» [SI-LIST] what level of overshoot is acceptalbe - WANG Zhenwei
» [SI-LIST] Re: Current Sense Resistor Measurement - Bill Grenoble
» [SI-LIST] Re: Current Sense Resistor Measurement - Tom Dagostino
» [SI-LIST] Re: Current Sense Resistor Measurement - Curt McNamara
» [SI-LIST] Re: Current Sense Resistor Measurement - Rose, Michael
» [SI-LIST] Re:： [SI-LIST] SDD21 and SDD11 - Lai Daniel
» [SI-LIST] Re: Current Sense Resistor Measurement - Jerry Chow
» [SI-LIST] Fwd: RFTI announcement - Ken Wyatt
» [SI-LIST] Re: surface roughness - Ken Cantrell
» [SI-LIST] Re: Current Sense Resistor Measurement - Wolfgang.Maichen
» [SI-LIST] Re: Current Sense Resistor Measurement - DAVID CUTHBERT
» [SI-LIST] Re: SDD21 and SDD11 - Wolfgang.Maichen
» [SI-LIST] AW: Re: SDD21 and SDD11 - Havermann, Gert
» [SI-LIST] Re： [SI-LIST] Re: SDD21 and SDD11 - Daniel Y.T. Lai
» [SI-LIST] Re: SDD21 and SDD11 - john lin
» [SI-LIST] Re: Current Sense Resistor Measurement - Wolfgang.Maichen
» [SI-LIST] Re: SDD21 and SDD11 - Wolfgang.Maichen
» [SI-LIST] Re: Current Sense Resistor Measurement - Danny Damhave
» [SI-LIST] Re: Current Sense Resistor Measurement - steve weir
» [SI-LIST] Re: Current Sense Resistor Measurement - Barry Rowland
» [SI-LIST] Re: Current Sense Resistor Measurement - steve weir
» [SI-LIST] Re: Current Sense Resistor Measurement - Alfred Lee
» [SI-LIST] Re: Current Sense Resistor Measurement - Orin Laney
» [SI-LIST] 回信： [SI-LIST] SDD21 and SDD11 - Daniel Y.T. Lai
» [SI-LIST] Re: Current Sense Resistor Measurement - ERIK KUNDRO
» [SI-LIST] Re: SDD21 and SDD11 - steve weir
» [SI-LIST] Re: Current Sense Resistor Measurement - steve weir
» [SI-LIST] Re: PCB stray capacitance - steve weir
» [SI-LIST] SDD21 and SDD11 - john lin
» [SI-LIST] Current Sense Resistor Measurement - ERIK KUNDRO
» [SI-LIST] PCB stray capacitance - Arulmurugan Pattusamy - ERS, HCL Tech
» [SI-LIST] Re: surface roughness - Scott McMorrow
» [SI-LIST] Re: surface roughness - Scott McMorrow
» [SI-LIST] #JItterPanel - input for DesignCon opening day panel - Ransom Stephens
» [SI-LIST] Re: surface roughness - Loyer, Jeff
» [SI-LIST] Web Seminars - EMI reduction, SI performance checking - Brad Brim
» [SI-LIST] Re: surface roughness - Scott McMorrow
» [SI-LIST] Asian IBIS Summit Presentations Available for Download! - Mirmak, Michael
» [SI-LIST] ANSYS Signal Integrity Product Manager Position Opening - Steve Pytel
» [SI-LIST] ANSYS SI Product Manager Position Opening - Steve Pytel
» [SI-LIST] Re: surface roughness - Oluwafemi, Olufemi B
» [SI-LIST] test - Heyfitch
» [SI-LIST] Re: 10 mm PCB - Massoud Shakeri
» [SI-LIST] Re: HFSS S-parameters... issues? - George Peterson
» [SI-LIST] Re: Damping of Cavity-Mode Resonances in PCB - Oprea, Dorin (Dorin)
» [SI-LIST] R: Re: AW: Re: 10 mm PCB - gianguida@xxxxxxxx
» [SI-LIST] Re: Damping of Cavity-Mode Resonances in PCB - Cristian Gozzi
» [SI-LIST] Re: AW: Re: 10 mm PCB - Wolfgang.Maichen
» [SI-LIST] AW: AW: Re: 10 mm PCB - Lenkisch, Andreas
» [SI-LIST] Re: surface roughness - Brian Rautio
» [SI-LIST] Re: surface roughness - Stefan Milnor
» [SI-LIST] Re: surface roughness - Scott McMorrow
» [SI-LIST] Re: Damping of Cavity-Mode Resonances in PCB - Scott McMorrow
» [SI-LIST] Re: Damping of Cavity-Mode Resonances in PCB - Jory McKinley
» [SI-LIST] Re: surface roughness - colin_warwick
» [SI-LIST] Re: surface roughness - Stefan Milnor
» [SI-LIST] Re: Damping of Cavity-Mode Resonances in PCB - Scott McMorrow
» [SI-LIST] Re: surface roughness - colin_warwick
» [SI-LIST] RF cable assembly - Heyfitch
» [SI-LIST] Re: Damping of Cavity-Mode Resonances in PCB - Grasso, Charles
» [SI-LIST] Re: Damping of Cavity-Mode Resonances in PCB - Jory McKinley
» [SI-LIST] Re: surface roughness - Scott McMorrow
» [SI-LIST] Re: Damping of Cavity-Mode Resonances in PCB - Scott McMorrow
» [SI-LIST] Re: surface roughness - colin_warwick
» [SI-LIST] Re: Damping of Cavity-Mode Resonances in PCB - steve weir
» [SI-LIST] Re: Damping of Cavity-Mode Resonances in PCB - Jory McKinley
» [SI-LIST] EMC Newsletter Delivered - Fall 2011 - Ken Wyatt
» [SI-LIST] Re: Damping of Cavity-Mode Resonances in PCB - Scott McMorrow
» [SI-LIST] Re: Damping of Cavity-Mode Resonances in PCB - Cristian Gozzi
» [SI-LIST] Re: Damping of Cavity-Mode Resonances in PCB - Jory McKinley
» [SI-LIST] Re: Damping of Cavity-Mode Resonances in PCB - steve weir
» [SI-LIST] Re: Damping of Cavity-Mode Resonances in PCB - Cristian Gozzi
» [SI-LIST] AW: Re: 10 mm PCB - Havermann, Gert
» [SI-LIST] Re: 10 mm PCB - Dudi Tash
» [SI-LIST] Re: 10 mm PCB - suresh kondepati
» [SI-LIST] 10 mm PCB - gianguida@xxxxxxxx
» [SI-LIST] Re: Damping of Cavity-Mode Resonances in PCB - Grasso, Charles
» [SI-LIST] Re: Damping of Cavity-Mode Resonances in PCB - Grasso, Charles
» [SI-LIST] Re: Damping of Cavity-Mode Resonances in PCB - steve weir
» [SI-LIST] Re: Damping of Cavity-Mode Resonances in PCB - Brad Brim
» [SI-LIST] Re: Damping of Cavity-Mode Resonances in PCB - steve weir
» [SI-LIST] Re: surface roughness - Scott McMorrow
» [SI-LIST] Re: Damping of Cavity-Mode Resonances in PCB - Jason Miller
» [SI-LIST] Re: Damping of Cavity-Mode Resonances in PCB - steve weir
» [SI-LIST] Re: Damping of Cavity-Mode Resonances in PCB - Brad Brim
» [SI-LIST] Damping of Cavity-Mode Resonances in PCB - Cristian Gozzi
» [SI-LIST] Re: surface roughness - Todd Westerhoff
» [SI-LIST] Re: surface roughness - colin_warwick
» [SI-LIST] Re: surface roughness - Yuriy Shlepnev
» [SI-LIST] Re: surface roughness - Cristian Gozzi
» [SI-LIST] Re: surface roughness - Loyer, Jeff
» [SI-LIST] Re: surface roughness - Hermann Ruckerbauer
» [SI-LIST] Re: surface roughness - steve weir
» [SI-LIST] surface roughness - nagachander . sing
» [SI-LIST] Senior SI open in Cisco Shanghai - ZhaoIris
» [SI-LIST] Re: problem with posting - Colin D Bennett
» [SI-LIST] Re: switch matrix - Iliya Zamek
» [SI-LIST] Re: switch matrix - alan . hiltonnickel
» [SI-LIST] Re: switch matrix - Mark Alexander
» [SI-LIST] Re: switch matrix - Gwen and Wolfgang
» [SI-LIST] Re: switch matrix - Peter . Pupalaikis
» [SI-LIST] switch matrix - Ming Li
» [SI-LIST] Re: Fwd: Im free now... - mukul pingley
» [SI-LIST] Re: permissable current density in PCB copper - john
» [SI-LIST] Re: Xilinx IBIS AMI models with Agilent ADS - colin_warwick
» [SI-LIST] Re: Xilinx IBIS AMI models with Agilent ADS - Hermann Ruckerbauer
» [SI-LIST] Re: Xilinx IBIS AMI models with Agilent ADS - signal integrity
» [SI-LIST] Re: Xilinx IBIS AMI models with Agilent ADS - Todd Westerhoff
» [SI-LIST] Re: Xilinx IBIS AMI models with Agilent ADS - Istvan Nagy
» [SI-LIST] RESEND: Re: Xilinx IBIS AMI models with Agilent ADS - colin_warwick
» [SI-LIST] Re: Xilinx IBIS AMI models with Agilent ADS - colin_warwick
» [SI-LIST] Re: AW: Re: Some reference on reference planes - steve weir
» [SI-LIST] Re: AW: Re: Some reference on reference planes - Smith, Larry
» [SI-LIST] Re: Xilinx IBIS AMI models with Agilent ADS - Todd Westerhoff
» [SI-LIST] Re: Trace Capacitance - Istvan Novak
» [SI-LIST] Re: permissable current density in PCB copper - Cristian Gozzi
» [SI-LIST] Re: Trace Capacitance - steve weir
» [SI-LIST] Trace Capacitance - johny leon
» [SI-LIST] Re: permissable current density in PCB copper - Scott McMorrow
» [SI-LIST] Re: permissable current density in PCB copper - Carrier, Patrick
» [SI-LIST] Re: Xilinx IBIS AMI models with Agilent ADS - Istvan Novak
» [SI-LIST] Re: Xilinx IBIS AMI models with Agilent ADS - Hermann Ruckerbauer
» [SI-LIST] Re: HFSS S-parameters... issues? - Cristian Gozzi
» [SI-LIST] Re: permissable current density in PCB copper - Istvan Nagy
» [SI-LIST] Re: AW: Re: Some reference on reference planes - Jory McKinley
» [SI-LIST] Re: AW: Re: Some reference on reference planes - Jory McKinley
» [SI-LIST] Xilinx IBIS AMI models with Agilent ADS - Istvan Nagy
» [SI-LIST] Re: permissable current density in PCB copper - Orin Laney
» [SI-LIST] permissable current density in PCB copper - Roopesh Badala
» [SI-LIST] Re: AW: Re: Some reference on reference planes - Scott McMorrow
» [SI-LIST] Re: AW: Re: Some reference on reference planes - Lee Ritchey
» [SI-LIST] Re: AW: Re: Some reference on reference planes - steve weir
» [SI-LIST] Re: HFSS S-parameters... issues? - Ken Cantrell
» [SI-LIST] Re: AW: Re: Some reference on reference planes - Lee Ritchey
» [SI-LIST] Re: HFSS S-parameters... issues? - George Peterson
» [SI-LIST] Re: HFSS S-parameters... issues? - Cristian Gozzi
» [SI-LIST] Asian IBIS Summit (Taipei) - Agenda - Bob Ross
» [SI-LIST] Re: Some reference on reference planes - Julia Nekrylova
» [SI-LIST] Re: Some reference on reference planes - Julia Nekrylova
» [SI-LIST] Re: HFSS S-parameters... issues? - Ken Cantrell
» [SI-LIST] Re: HFSS S-parameters... issues? - George Peterson
» [SI-LIST] Re: HFSS S-parameters... issues? - Scott McMorrow
» [SI-LIST] HFSS S-parameters... issues? - George Peterson
» [SI-LIST] Re: AW: Re: Some reference on reference planes - Scott McMorrow
» [SI-LIST] Re: about the standards of 25Gbps - Vinu Arumugham
» [SI-LIST] Re: AW: Re: Some reference on reference planes - steve weir
» [SI-LIST] Re: AW: Re: Some reference on reference planes - Lee Ritchey
» [SI-LIST] AW: Re: about the standards of 25Gbps - Havermann, Gert
» [SI-LIST] Re: about the standards of 25Gbps - selina lin
» [SI-LIST] Re: about the standards of 25Gbps - selina lin
» [SI-LIST] Re: Multi-line S-parameters to RLGC matrices - elie issa
» [SI-LIST] Re: Multi-line S-parameters to RLGC matrices - elie issa
» [SI-LIST] Re: AW: Re: Some reference on reference planes - Smith, Larry
» [SI-LIST] Asian IBIS Summit (Yokohama) - Agenda - Bob Ross
» [SI-LIST] Multi-line S-parameters to RLGC matrices - John
» [SI-LIST] Re: about the standards of 25Gbps - Vinu Arumugham
» [SI-LIST] Re: Wirebond package VS Flipchip package - Scott McMorrow
» [SI-LIST] test - elie issa
» [SI-LIST] Re: about the standards of 25Gbps - Zabinski, Patrick
» [SI-LIST] about the standards of 25Gbps - selina lin
» [SI-LIST] AW: AW: AW: Re: Some reference on reference planes - Havermann, Gert
» [SI-LIST] AW: AW: Re: Some reference on reference planes - Havermann, Gert
» [SI-LIST] Re: Wirebond package VS Flipchip package - steve weir
» [SI-LIST] Wirebond package VS Flipchip package - Devis . Lu
» [SI-LIST] Re: The Steve - Lee Ritchey
» [SI-LIST] Re: AW: Re: Some reference on reference planes - Lee Ritchey
» [SI-LIST] Re: AW: Re: Some reference on reference planes - Mark Grobman
» [SI-LIST] 11/18 Free EMC Technical Webinar: Near-Fied EMI Detection - Eriko Yamato
» [SI-LIST] Re: DIMM-connector frequency characterization info? - Ray Anderson
» [SI-LIST] Re: DIMM-connector frequency characterization info? - Hermann Ruckerbauer
» [SI-LIST] Re: DIMM-connector frequency characterization info? - Robert Myoung
» [SI-LIST] DIMM-connector frequency characterization info? - Stephanie Goedecke
» [SI-LIST] AW: IBIS Rx Single-Ended vs Differential - Havermann, Gert
» [SI-LIST] IBIS Rx Single-Ended vs Differential - Jim Kulyk
» [SI-LIST] Re: The Steve - elie issa
» [SI-LIST] The Steve - elie issa
» [SI-LIST] Re: Calculating S-parameters with Tek TDR + Iconnect - elie issa
» [SI-LIST] AW: Re: Some reference on reference planes - Havermann, Gert
» [SI-LIST] IEEE Workshop on Signal and Power Integrity - SPI2012 - antonio maffucci
» [SI-LIST] Re: Some reference on reference planes - steve weir
» [SI-LIST] Re: Some reference on reference planes - Mark Grobman
» [SI-LIST] Asian IBIS Summit (Shanghai) - Agenda - Bob Ross
» [SI-LIST] Re: Some reference on reference planes - Jory McKinley
» [SI-LIST] Re: Some reference on reference planes - Mikhail Matusov
» [SI-LIST] Re: Some reference on reference planes - Rick Collins
» [SI-LIST] Re: Some reference on reference planes - Mark Grobman
» [SI-LIST] Re: Some reference on reference planes - Rick Collins
» [SI-LIST] Re: Some reference on reference planes - N. Paul Taddonio
» [SI-LIST] Re: Some reference on reference planes - hanymhfahmy
» [SI-LIST] Some reference on reference planes - Mark Grobman
» [SI-LIST] SI-PI Seminars (next week) - Brad Brim
» [SI-LIST] Re: Hspice model versus spice model - Muranyi, Arpad
» [SI-LIST] Re: Hspice model versus spice model - Lynne D. Green
» [SI-LIST] Re: Hspice model versus spice model - steve weir
» [SI-LIST] Hspice model versus spice model - Bernadine Splettstoeszer
» [SI-LIST] Asian IBIS Summit (Taipei) - Fifth Announcement - Bob Ross
» [SI-LIST] Re: PCB parastic extraction - elie issa
» [SI-LIST] Re: PCB parastic extraction - sunil bharadwaz
» [SI-LIST] Re: PCB parastic extraction - Cristian Gozzi
» [SI-LIST] Re: PCB parastic extraction - Brad Brim
» [SI-LIST] Re: Looking for books, classes or instructions on microvias for hi-layer count designs - Lee Ritchey
» [SI-LIST] Re: PCB parastic extraction - Andro Radchenko
» [SI-LIST] Re: [suspected spam] PCB parastic extraction - steve weir
» [SI-LIST] Re: [suspected spam] PCB parastic extraction - Ing. Giancarlo Guida
» [SI-LIST] Re: [suspected spam] PCB parastic extraction - steve weir
» [SI-LIST] Re: PCB parastic extraction - hanymhfahmy
» [SI-LIST] PCB parastic extraction - sunil bharadwaz
» [SI-LIST] Apple - brent Jacobs
» [SI-LIST] Re: Looking for books, classes or instructions on microvias for hi-layer count designs - Viklund, Per
» [SI-LIST] Re: Looking for books, classes or instructions on microvias for hi-layer count designs - Mike Sharpes (msharpes)
» [SI-LIST] Looking for books, classes or instructions on microvias for hi-layer count designs - kevin kimball
» [SI-LIST] Re: PCB Stackup Design Class by Lee Ritchey - Lee Ritchey
» [SI-LIST] two lectures by Eric Bogatin, San Jose and Boulder - Eric Bogatin
» [SI-LIST] Asian IBIS Summit (Yokohama) - Fourth Announcement - Bob Ross
» [SI-LIST] AW: Calculating S-parameters with Tek TDR + Iconnect - Havermann, Gert
» [SI-LIST] Signal Integrity position - Dev Malladi
» [SI-LIST] Re: Calculating S-parameters with Tek TDR + Iconnect - elie issa
» [SI-LIST] Re: Sad Trip.............(Haixiao Weng) - Haixiao Weng
» [SI-LIST] Re: Sad Trip.............(Haixiao Weng) - steve weir
» [SI-LIST] Re: Sad Trip.............(Haixiao Weng) - alfred1520list
» [SI-LIST] Re: Calculating S-parameters with Tek TDR + IConnect - Tom Dagostino
» [SI-LIST] Job Opportunity at Altera - Mayra Sarmiento
» [SI-LIST] Calculating S-parameters with Tek TDR + Iconnect - Juan G Fuentes
» [SI-LIST] Re: Sad Trip.............(Haixiao Weng) - johndp
» [SI-LIST] How close is dangerous for Waveport excitation in HFSS? - Tesla
» [SI-LIST] Re: Sad Trip.............(Haixiao Weng) - steve weir
» [SI-LIST] Sad Trip.............(Haixiao Weng) - Haixiao Weng
» [SI-LIST] re: [SI-LIST] 答复: [SI-LIST] Re: "Ground" strips between LVDS pairs - yu . yanfeng
» [SI-LIST] 答复: [SI-LIST] Re: "Ground" strips between LVDS pairs - Shao, Peng
» [SI-LIST] Re: Mode conversion question *** restated - steve weir
» [SI-LIST] Re: Mode conversion question *** restated - Yuriy Shlepnev
» [SI-LIST] WebEx and GoToMeeting services for engineering meetings - Doug Smith
» [SI-LIST] Re: power supply output series jumper - alan . hiltonnickel
» [SI-LIST] Re: 10 Layer Stack-up board/TWR PCB - Rick Collins
» [SI-LIST] Bleeding static charge during testing - Doug Smith
» [SI-LIST] Re: power supply output series jumper - Rick Collins
» [SI-LIST] Mode conversion question *** restated - Doug Brooks
» [SI-LIST] Re: power supply output series jumper - Cosmin Iorga
» [SI-LIST] Re: power supply output series jumper - steve weir
» [SI-LIST] power supply output series jumper - Harwood, Morton (GE Aviation, US)
» [SI-LIST] Re: Mode conversion question - Joseph . Schachner
» [SI-LIST] Re: Mode conversion question - Kevin G. Rhoads
» [SI-LIST] Re: How to solve short circuit issues in high dense pcbs - johndp
» [SI-LIST] Re: 10 Layer Stack-up board/TWR PCB - Jayasuryan KG
» [SI-LIST] Re: 10 Layer Stack-up board/TWR PCB - Doug Smith
» [SI-LIST] Re: OT: Mobile apps for engineers - Martin Euredjian
» [SI-LIST] Re: OT: Mobile apps for engineers - Martin Euredjian
» [SI-LIST] Re: How to solve short circuit issues in high dense pcbs - Doug Smith
» [SI-LIST] Re: 10 Layer Stack-up board/TWR PCB - Doug Smith
» [SI-LIST] Re: Mode conversion question - steve weir
» [SI-LIST] Re: Mode conversion question - Doug Smith
» [SI-LIST] Re: Mode conversion question - Ken Cantrell
» [SI-LIST] Re: Mode conversion question - Siming Pan
» [SI-LIST] Re: OT: Mobile apps for engineers - alfred1520list
» [SI-LIST] Re: 10 Layer Stack-up board/TWR PCB - Lee Ritchey
» [SI-LIST] Re: How to solve short circuit issues in high dense pcbs - Pommerenke, David
» [SI-LIST] Re: Mode conversion question - Kevin G. Rhoads
» [SI-LIST] Re: 10 Layer Stack-up board/TWR PCB - asparky
» [SI-LIST] OT: Mobile apps for engineers - Martin Euredjian
» [SI-LIST] Re: 10 Layer Stack-up board/TWR PCB - Jory McKinley
» [SI-LIST] Re: Mode conversion question - Orin Laney
» [SI-LIST] Re: 10 Layer Stack-up board/TWR PCB - Lee Ritchey
» [SI-LIST] Re: How to solve short circuit issues in high dense pcbs - Danny Damhave
» [SI-LIST] Mode conversion question - Doug Brooks
» [SI-LIST] Re: 10 Layer Stack-up board/TWR PCB - Jory McKinley
» [SI-LIST] Re: 10 Layer Stack-up board/TWR PCB - Filion, Marc-Andre
» [SI-LIST] Re: 10 Layer Stack-up board/TWR PCB - Rick Collins
» [SI-LIST] Re: How to solve short circuit issues in high dense pcbs - N. Paul Taddonio
» [SI-LIST] Looking for FPGA on-die PDN Frequency Characteristic Measurement Test Cases - Cosmin Iorga