Posts for si-list, 11-2005

Browse: Last Month: 10-2005 Main Archive Page Next Month: 12-2005

» [SI-LIST] SI Job Opening - Extreme Networks -
» [SI-LIST] Re: NEXT and FEXT: Question on relative levels -
» [SI-LIST] Re: NEXT and FEXT: Question on relative levels -
» [SI-LIST] Re: NEXT and FEXT: Question on relative levels -
» [SI-LIST] Re: NEXT and FEXT: Question on relative levels -
» [SI-LIST] Re: NEXT and FEXT: Question on relative levels -
» [SI-LIST] Re: NEXT and FEXT: Question on relative levels -
» [SI-LIST] Re: NEXT and FEXT: Question on relative levels -
» [SI-LIST] Re: NEXT and FEXT: Question on relative levels -
» [SI-LIST] Re: DC resistance of the Power Supply on PCB -
» [SI-LIST] Re: NEXT and FEXT: Question on relative levels -
» [SI-LIST] Re: Time domain AMS-SI tools -
» [SI-LIST] Immediate Package Characterization Engineer Opening at Xilinx San Jose -
» [SI-LIST] Re: ??: NEXT and FEXT: Question on relative levels -
» [SI-LIST] Re: ??: NEXT and FEXT: Question on relative levels -
» [SI-LIST] Re: Time domain AMS-SI tools -
» [SI-LIST] Re: DC resistance of the Power Supply on PCB -
» [SI-LIST] Re: Bit pattern for high speed serial link simulation -
» [SI-LIST] Re: DC resistance of the Power Supply on PCB -
» [SI-LIST] Re: DC resistance of the Power Supply on PCB -
» [SI-LIST] DC resistance of the Power Supply on PCB -
» [SI-LIST] Re: Time domain AMS-SI tools -
» [SI-LIST] Re: Time domain AMS-SI tools -
» [SI-LIST] Time domain AMS-SI tools -
» [SI-LIST] 回复： NEXT and FEXT: Question on relative levels -
» [SI-LIST] Re: NEXT and FEXT: Question on relative levels -
» [SI-LIST] Re: Bit pattern for high speed serial link simulation -
» [SI-LIST] Re: Bit pattern for high speed serial link simulation -
» [SI-LIST] Re: Bit pattern for high speed serial link simulation -
» [SI-LIST] Re: Bit pattern for high speed serial link simulation -
» [SI-LIST] 'unsubscribe' -
» [SI-LIST] Agenda - Asian IBIS Summit -
» [SI-LIST] unsubscribe -
» [SI-LIST] Job Opening Texas Instruments - Dalla, TX -
» [SI-LIST] Re: Bit pattern for high speed serial link simulation -
» [SI-LIST] Re: Bit pattern for high speed serial link simulation -
» [SI-LIST] Re: Bit pattern for high speed serial link simulation -
» [SI-LIST] Re: Bit pattern for high speed serial link simulation -
» [SI-LIST] NEXT and FEXT: Question on relative levels -
» [SI-LIST] Re: Bit pattern for high speed serial link simulation -
» [SI-LIST] Re: Bit pattern for high speed serial link simulation -
» [SI-LIST] PSpice to HSpice -
» [SI-LIST] Re: Effective impedance of a uniformly loaded bus -
» [SI-LIST] Re: Effective impedance of a uniformly loaded bus -
» [SI-LIST] Re: Bit pattern for high speed serial link simulation -
» [SI-LIST] Re: Bit pattern for high speed serial link simulation -
» [SI-LIST] Re: Bit pattern for high speed serial link simulation -
» [SI-LIST] Re: Bit pattern for high speed serial link simulation -
» [SI-LIST] Bit pattern for high speed serial link simulation -
» [SI-LIST] Re: Effective impedance of a uniformly loaded bus -
» [SI-LIST] Re: Effective impedance of a uniformly loaded bus -
» [SI-LIST] Re: Effective impedance of a uniformly loaded bus -
» [SI-LIST] Re: HSPICE **error**: unknown data card: -
» [SI-LIST] Re: HSPICE **error**: unknown data card: -
» [SI-LIST] EMC test -
» [SI-LIST] Effective impedance of a uniformly loaded bus -
» [SI-LIST] Re: HELP!! SpecctraQuest is GOOD/BAD Tool for Boar -
» [SI-LIST] Re: Plastic solder balls -
» [SI-LIST] Re: Two SDRAM ICs -
» [SI-LIST] Re: the right way to choose the scrambler -
» [SI-LIST] HSPICE **error**: unknown data card: -
» [SI-LIST] query please -
» [SI-LIST] query please -
» [SI-LIST] Re: query please -
» [SI-LIST] Re: 50 ohms cable model -
» [SI-LIST] Re: the right way to choose the scrambler -
» [SI-LIST] Re: HELP!! SpecctraQuest is GOOD/BAD Tool for Boar -
» [SI-LIST] the right way to choose the scrambler -
» [SI-LIST] query please -
» [SI-LIST] Re: buffer selection -
» [SI-LIST] Re: Raw cable construction and twisted pairs -
» [SI-LIST] Raw cable construction and twisted pairs -
» [SI-LIST] Re: buffer selection -
» [SI-LIST] Re: 50 ohms cable model -
» [SI-LIST] Re: HELP!! SpecctraQuest is GOOD/BAD Tool for Boar d Level Simulation < 400 MT/s??? -
» [SI-LIST] Re: 50 ohms cable model -
» [SI-LIST] Re: 50 ohms cable model -
» [SI-LIST] Re: Caution Spam:Re: HELP!! SpecctraQuest is GOOD/BAD Tool for Boar d Level Simulation < 400 MT/s??? -
» [SI-LIST] 50 ohms cable model -
» [SI-LIST] Re: HELP!! SpecctraQuest is GOOD/BAD Tool for Boar d Level Simulation < 400 MT/s??? -
» [SI-LIST] Re: HELP!! SpecctraQuest is GOOD/BAD Tool for Board Level Simulation < 400 MT/s??? -
» [SI-LIST] buffer selection -
» [SI-LIST] Re: HELP!! SpecctraQuest is GOOD/BAD Tool for Boar d Level Simulation < 400 MT/s??? -
» [SI-LIST] Re: HELP!! SpecctraQuest is GOOD/BAD Tool for Boar d Level Simulation < 400 MT/s??? -
» [SI-LIST] Re: HELP!! SpecctraQuest is GOOD/BAD Tool for Boar d Level Simulation < 400 MT/s??? -
» [SI-LIST] Re: HELP!! SpecctraQuest is GOOD/BAD Tool for Board Level Simulation < 400 MT/s??? -
» [SI-LIST] Re: HELP!! SpecctraQuest is GOOD/BAD Tool for Boar d Level Simulation < 400 MT/s??? -
» [SI-LIST] Two SDRAM ICs -
» [SI-LIST] Re: HELP!! SpecctraQuest is GOOD/BAD Tool for Board Level Simulation < 400 MT/s??? -
» [SI-LIST] Re: HELP!! SpecctraQuest is GOOD/BAD Tool for Board Level Simulation < 400 MT/s??? -
» [SI-LIST] Re: HELP!! SpecctraQuest is GOOD/BAD Tool for Board Level Simulation < 400 MT/s??? -
» [SI-LIST] Re: HELP!! SpecctraQuest is GOOD/BAD Tool for Board Level Simulation < 400 MT/s??? -
» [SI-LIST] Re: HELP!! SpecctraQuest is GOOD/BAD Tool for Board Level Simulation < 400 MT/s??? -
» [SI-LIST] Re: HELP!! SpecctraQuest is GOOD/BAD Tool for Board Level Simulation < 400 MT/s??? -
» [SI-LIST] HELP!! SpecctraQuest is GOOD/BAD Tool for Board Level Simulation < 400 MT/s??? -
» [SI-LIST] Re: SDRAM read problem -
» [SI-LIST] Re: SDRAM read problem -
» [SI-LIST] Re: Trace Width -
» [SI-LIST] Trace Width -
» [SI-LIST] Re: Test our 10 GHz frequency divider and keep the prototype unit?--SOLD -
» [SI-LIST] Spice (scope rules) syntax of parameter passing in .subckt -
» [SI-LIST] RTL8100BL and MINI PCI 124 ibis models -
» [SI-LIST] European IBIS Summit At DATe 2006 - First Call for Paper/Call for Participation -
» [SI-LIST] Re: Copper atom density -
» [SI-LIST] Immediate Package Characterization Engineer Opening at Xilinx San Jose -
» [SI-LIST] SDRAM read problem -
» [SI-LIST] Asian IBIS Summit Sixth Announcement -
» [SI-LIST] Re: Copper atom density -
» [SI-LIST] Test our 10 GHz frequency divider and keep the prototype unit? -
» [SI-LIST] Re: Copper atom density -
» [SI-LIST] Re: Plastic solder balls -
» [SI-LIST] Query on termination techniques -
» [SI-LIST] Re: Copper atom density -
» [SI-LIST] Re: Copper atom density -
» [SI-LIST] Re: Copper atom density -
» [SI-LIST] Copper atom density -
» [SI-LIST] Re: Single ended s-parameters of a differential mircost rip line -
» [SI-LIST] Re: PCI-E, Zdiff and Er -
» [SI-LIST] Re: Antw: current density -
» [SI-LIST] Re: PCI-E, Zdiff and Er -
» [SI-LIST] Antw: current density -
» [SI-LIST] current density -
» [SI-LIST] PCI-E, Zdiff and Er -
» [SI-LIST] Plastic solder balls -
» [SI-LIST] Modeling questions -
» [SI-LIST] Re: Single ended s-parameters of a differential mir cost rip line -
» [SI-LIST] Re: Single ended s-parameters of a differential mircost rip line -
» [SI-LIST] Re: Resistor packs, SI issues? -
» [SI-LIST] Re: Resistor packs, SI issues? -
» [SI-LIST] Re: Resistor packs, SI issues? -
» [SI-LIST] Re: Resistor packs, SI issues? -
» [SI-LIST] Re: Single ended s-parameters of a differential mircostrip line -
» [SI-LIST] Single ended s-parameters of a differential mircostrip line -
» [SI-LIST] Resistor packs, SI issues? -
» [SI-LIST] Re: PCI/PCIX minimum lenghts? -
» [SI-LIST] VNA choice -
» [SI-LIST] Re: BGA Fan Out -
» [SI-LIST] Re: PCI/PCIX minimum lenghts? -
» [SI-LIST] Re: BGA Fan Out -
» [SI-LIST] BGA Fan Out -
» [SI-LIST] Re: PCI/PCIX minimum lenghts? -
» [SI-LIST] Signal Integrity Position -
» [SI-LIST] Re: PCI/PCIX minimum lenghts? -
» [SI-LIST] Looking for SI job in Southern California -
» [SI-LIST] Re: PCI/PCIX minimum lenghts? -
» [SI-LIST] Re: PCI/PCIX minimum lenghts? -
» [SI-LIST] Re: PCI/PCIX minimum lenghts? -
» [SI-LIST] Re: ESR too low? -
» [SI-LIST] PCI/PCIX minimum lenghts? -
» [SI-LIST] Re: ESR too low? -
» [SI-LIST] Re: ESR too low? -
» [SI-LIST] Re: ESR too low? -
» [SI-LIST] Re: ESR too low? -
» [SI-LIST] Re: ESR too low? -
» [SI-LIST] Re: ESR too low? -
» [SI-LIST] Re: ESR too low? -
» [SI-LIST] Re: ESR too low? -
» [SI-LIST] Re: Jitter Analysis Using Spice. -
» [SI-LIST] Re: ESR too low? -
» [SI-LIST] Re: ESR too low? -
» [SI-LIST] Jitter Analysis Using Spice. -
» [SI-LIST] Re: TEK or ex-HP, that is the question; or FLY WITH THE SIGNAL -
» [SI-LIST] Re: ESR too low? -
» [SI-LIST] Asian IBIS Summit Fifth Announcement -
» [SI-LIST] Re: ESR too low? -
» [SI-LIST] Re: ESR too low? -
» [SI-LIST] Re: ESR too low? -
» [SI-LIST] Re: ESR too low? -
» [SI-LIST] Re: ESR too low? -
» [SI-LIST] IEEE EMCS Santa Clara Valley (SCV) Chapter meeting- November 8, 2005 -
» [SI-LIST] ESR too low? -
» [SI-LIST] Re: Transition time constraint for TSMC 0.18 design -
» [SI-LIST] Re: Question on EMI radiated power -
» [SI-LIST] Re: Question on EMI radiated power -
» [SI-LIST] Re: Question on EMI radiated power -
» [SI-LIST] Re: Question on EMI radiated power -
» [SI-LIST] Re: TEK or ex-HP, that is the question -
» [SI-LIST] Si and EMC troubleshooting method -
» [SI-LIST] Re: Question on EMI radiated power -
» [SI-LIST] Transition time constraint for TSMC 0.18 design -
» [SI-LIST] Re: Question on EMI radiated power -
» [SI-LIST] Re: Question on EMI radiated power -
» [SI-LIST] Re: Question on EMI radiated power -
» [SI-LIST] Question on EMI radiated power -
» [SI-LIST] Modeling questions -
» [SI-LIST] Job Opening -
» [SI-LIST] Re: problem - can't simulate Spice in Hyperlynx -
» [SI-LIST] Re: problem - can't simulate Spice in Hyperlynx -
» [SI-LIST] Re: problem - can't simulate Spice in Hyperlynx -
» [SI-LIST] problem - can't simulate Spice in Hyperlynx -
» [SI-LIST] Re: REPOST: SI Question 3 of 3: Power plane fingers over split in ground plane -
» [SI-LIST] Re: REPOST: SI Question 1 of 3: "Quiet" lines over split in ground plane -
» [SI-LIST] Re: High-speed serial data transfer -
» [SI-LIST] Re: Can L12 ever exceed L1 or L2 ?? -